Hardware Validation Engineer, Sr Staff

Synopsys, Inc.; Ottawa; On-site; CAD 130,000 - 165,000; Full time

Job summary

Synopsys in Ottawa, Ontario seeks a senior hardware designer to validate memory-interface IP on boards and characterize high-speed interfaces. You will work in a lab-focused environment, bridging silicon behavior with real-world board performance.

You will analyze S-parameters, eye diagrams, and crosstalk, route JTAG/I2C/SPI/UART, and mentor engineers while contributing to design guidelines and faster bring-up of IP. This role is on-site in Nepean.

Qualifications

• Bachelor's or Master's in Electrical Engineering or equivalent hands-on experience.
• 6-8+ years in hardware design and validation for high-speed digital/mixed-signal systems.
• Expert Cadence Allegro proficiency for schematic capture and PCB layout.
• Deep knowledge of S-parameters, impedance, crosstalk, and return loss.
• Experience debugging with logic analyzers, oscilloscopes, VNAs, and spectrum analyzers.
• Experience with JTAG, I2C, SPI, UART interfaces and routing best practices.

Responsibilities

• Design, layout, and validate PCBs in Cadence Allegro for memory interface IP characterization.
• Analyze high-speed signal behavior using S-parameters, eye diagrams, and crosstalk simulations.
• Route and validate JTAG, I2C, SPI, and UART interfaces with attention to timing margins.
• Debug board-level issues using logic analyzers, oscilloscopes, and protocol analyzers.
• Review design files with cross-functional teams and teach routing and decoupling best practices.
• Interpret SPICE, IBIS, and channel analysis tool waveforms to validate analog/mixed-signal performance.
• Drive root cause analysis on validation failures spanning silicon, board, or environment.

Skills

Cadence Allegro

Signal integrity

High-speed digital

PCB layout

JTAG/I2C/SPI/UART

Bench instrumentation

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Allegro

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years turning design files into real boards that work, not just pass DRC, actually work when you power them up and start probing signals. You know that a clean schematic means nothing if the layout introduces crosstalk that kills your eye diagram.

You live in the space between design intent and physical reality. When a signal integrity simulation says one thing and the scope says another, you do not pick a side, you figure out which assumption was wrong. You have routed enough high-speed interfaces to know that JTAG chains fail for predictable reasons and that S-parameters tell a story if you know how to read them.

At Synopsys, you will validate memory interface IP where the margin between working silicon and a customer escalation is measured in picoseconds, and your board-level work is what closes that gap.

What You'll Be Doing

• Design, layout, and validate PCBs in Cadence Allegro for memory interface IP characterization and customer reference designs
• Analyze high-speed signal behavior using S-parameters, eye diagrams, and crosstalk simulations to ensure signal integrity across multi-gigabit interfaces
• Route and validate communication interfaces including JTAG, I2C, and other low-speed control planes with attention to noise immunity and timing margins
• Debug board-level issues using logic analyzers, oscilloscopes, and protocol analyzers to isolate failures across silicon, firmware, layout, and test setup
• Review design files and layout with cross-functional teams, teaching best practices for routing, decoupling, and design rule adherence
• Interpret simulation waveforms from SPICE, IBIS, and channel analysis tools to validate analog and mixed-signal circuit performance
• Drive root cause analysis on validation failures, determining whether issues stem from silicon behavior, board design, or environmental factors

The Impact You Will Have

• Your board designs will serve as the validation platform for Synopsys memory IP used in customer production deployments across automotive, mobile, and data center applications
• The signal integrity work you do will directly inform design guidelines that prevent customer respins and reduce time to market
• Your debug findings will feed back into silicon design teams, closing the loop between simulated and measured performance
• The review practices you establish will raise the quality bar for how the team evaluates layout and catches issues before boards are fabricated
• Your ability to isolate failures quickly will accelerate bring-up schedules and get IP into customer hands faster
• The reference designs you validate will become the foundation for how customers integrate Synopsys IP into their own systems
• Your mentorship will build the next generation of validation engineers who understand the full stack from transistor to trace

What You'll Need

• Bachelor's or Master's in Electrical Engineering, Electronics Engineering, or equivalent hands-on experience
• 6-8+ years of Hardware design and validation experience with a focus on high-speed digital and mixed-signal systems
• Expert-level proficiency in Cadence Allegro for schematic capture, PCB layout, and constraint-driven design
• Deep understanding of signal integrity concepts including S-parameters, impedance control, crosstalk, intersymbol interference, and return loss
• Strong knowledge of analog IC circuit design and the ability to analyze SPICE simulation waveforms and correlate them to measured behavior
• Hands-on experience debugging hardware using logic analyzers, oscilloscopes, VNAs, spectrum analyzers, protocol analyzers, and other bench instrumentation
• Experience with communication interfaces such as JTAG, I2C, SPI, and UART, including routing best practices and protocol-level debug
• Knowledge of PCB stack-up design and high-speed materials.

Who You Are

• You drive complex technical problems independently across multiple disciplines without waiting for direction
• You diagnose whether a failure is silicon, firmware, board, or test setup and make the call quickly

• You translate technical findings into clear recommendations that design, firmware, and customer teams can act on
• You mentor junior engineers through their first characterization projects without taking over the work
• You push back when validation coverage is thin or root cause stops at correlation instead of causation

The Team You'll Be Part Of

You will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.