Validation / Verification Eng, Staff Engineer

Synopsys, Inc.; Ottawa; On-site; CAD 110,000 - 170,000; Full time

Job summary

Synopsys, Inc. in Ottawa seeks a senior hardware design and validation engineer to validate memory interface IP and ensure signal integrity across multi-gigabit interfaces.

You will collaborate with firmware and design teams, perform rigorous root-cause analysis, and establish best practices for routing, power distribution, and test configurations to accelerate product readiness. The role requires a strong background in high-speed digital design and a hands-on approach to bench validation.

Qualifications

• Degree in Electrical/Electronics engineering or equivalent.
• 6-8+ years of hardware design and validation experience.
• Expert-level Cadence Allegro for schematic and PCB layout.

Responsibilities

• Design, layout, and validate PCBs for memory interface IP characterization and reference implementations.
• Perform signal integrity analysis using S-parameters, eye diagrams, and crosstalk simulations.
• Debug hardware with logic analyzers, oscilloscopes, and protocol analyzers to isolate root causes.
• Conduct design reviews to establish best practices for routing and power distribution.
• Execute root cause analysis to determine silicon, board, or environmental origins.

Skills

High-speed design

Signal integrity

Cadence Allegro

Hardware debugging

JTAG I2C SPI UART

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Vector Network Analyzer

Oscilloscope

Protocol Analyzers

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have built a career designing and validating hardware systems that must perform reliably in production environments, not simply pass design rule checks. Your experience has taught you that schematic correctness is only the beginning; layout decisions determine whether signal integrity holds under real operating conditions.

You work at the intersection of simulation and measurement. When analytical models diverge from bench results, you systematically identify which assumptions require revision. Years of routing high-speed interfaces have given you the expertise to anticipate common failure modes in JTAG chains and interpret S-parameter data with precision.

Diagnostic work is central to your technical approach. You excel at distinguishing between silicon-level issues, PCB layout defects, and test environment artifacts. Your methodology is rigorous, your conclusions are defensible, and your recommendations are grounded in measured data.

At Synopsys, you will validate memory interface IP where timing margins are measured in picoseconds and your board-level engineering directly determines product quality and customer success.

What You'll Be Doing

• Design, layout, and validate printed circuit boards in Cadence Allegro for memory interface IP characterization and customer reference implementations
• Perform signal integrity analysis using S-parameters, eye diagrams, and crosstalk simulations to verify performance across multi-gigabit interfaces
• Debug hardware systems using logic analyzers, oscilloscopes, and protocol analyzers to isolate root causes across silicon, firmware, layout, and test configurations
• Conduct design reviews with cross-functional teams to establish best practices for routing, power distribution, and design constraint compliance
• Execute root cause analysis on validation failures to determine whether issues originate from silicon behavior, board design, or environmental conditions

The Impact You Will Have

• Your board designs will provide the validation infrastructure for Synopsys memory IP deployed in automotive, mobile, and data center customer applications
• Your signal integrity analysis will inform design guidelines that reduce customer design iterations and accelerate time to market
• Your validation findings will provide critical feedback to silicon design teams, ensuring alignment between simulated and measured performance
• Your technical reviews will establish quality standards for layout evaluation and early detection of design issues
• Your diagnostic capabilities will reduce bring-up cycle times and expedite IP delivery to customers
• Your reference designs will serve as integration templates for customers implementing Synopsys IP in production systems

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or equivalent professional experience
• 6-8+ years of hardware design and validation experience focused on high-speed digital and mixed-signal systems
• Expert-level proficiency in Cadence Allegro for schematic capture, PCB layout, and constraint-driven design
• Comprehensive understanding of signal integrity principles including S-parameters, impedance control, crosstalk, intersymbol interference, and return loss
• Demonstrated experience debugging hardware using logic analyzers, oscilloscopes, vector network analyzers, spectrum analyzers, and protocol analyzers
• Working knowledge of communication interfaces including JTAG, I2C, SPI, and UART, with understanding of routing requirements and protocol-level diagnostics

Who You Are

• You independently manage complex technical problems across multiple engineering disciplines with minimal supervision
• You systematically determine whether failures originate from silicon, firmware, board design, or test setup and reach conclusions efficiently
• You communicate technical findings clearly to design, firmware, and customer-facing teams in actionable formats
• You provide technical guidance to junior engineers while allowing them to develop ownership of their work
• You challenge incomplete validation coverage and ensure root cause analysis proceeds beyond surface-level correlation

The Team You'll Be Part Of

You will join the Nepean laboratory team responsible for validating Synopsys' memory interface IP portfolio. This is a laboratory-based engineering environment where you will collaborate with firmware and design engineering groups to advance IP from initial silicon bring-up through production release. The team functions at the critical interface between design specifications and measured silicon performance, and your contributions will directly influence product readiness and customer deployments.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.