Lead VHDL RTL FPGA Engineer – Critical Infra

Schweitzer Engineering Laboratories (SEL); Burnaby; On-site; CAD 106,000 - 158,000; Full time

Benefits offered by this job

RRSP contributions

Health insurance

Paid holidays

Vacation days

Sick days

Parental leave

Engineering development programs

Wellness / adoption assistance

Job summary

Schweitzer Engineering Laboratories (SEL) in Burnaby, BC is seeking a Lead Engineer focused on VHDL RTL digital logic design to guide our R&D Communications product group. You will contribute to SONET/VSN multiplexers, Ethernet gateways, and network timing systems while mentoring teammates and shaping architecture.

This role requires hands-on RTL design for FPGAs, strong documentation, and collaboration with product managers to deliver safe, reliable, and economical electric power protection

Qualifications

• B.S. degree in Electrical Engineering, related discipline, or equivalent combination of education and experience.
• 5+ years of combined experience in RTL Digital Design with FPGAs using VHDL/Verilog and related toolchains.
• Experience with Xilinx, Intel FPGA (Altera), Microchip (Microsemi/Actel), Lattice Semiconductor Tools.
• Firmware Design with FPGA SOCs/Microprocessors using C/C++.
• Simulation, Synthesis and Timing Analysis of Digital Logic.
• Functional verification of RTL Digital Logic.
• Ability to work cooperatively in a team environment; mentor others; strong writing and documentation.
• Background check satisfactory to SEL; negative drug test.

Responsibilities

• Serving as technical lead on complex VHDL RTL digital logic projects.
• Creating and maintaining internal RTL design documentation.
• Writing test plans and developing test harnesses/stimulus for RTL functional verification.
• Preparing design and system level specifications.
• Participating or moderating peer reviews of designs, documentation and test plans.
• Providing and maintaining accurate project plans and labor estimates.
• Working closely with product managers on new product concepts and enhancements.
• Engaging with cross-discipline teams to deliver world-class products for critical infrastructure.
• (3-5 essential duties and responsibilities as described)

Skills

RTL Digital Design

VHDL/Verilog

FPGAs

C/C++

Synthesis & Timing Analysis

Functional verification

Mentoring

Teamwork

Technical writing

FPGA toolchains

Education

B.S. in Electrical Engineering

Tools

Xilinx Tools

Intel FPGA Tools (Altera)

Microchip Tools

Lattice Tools

JIRA

Confluence

GitHub

Job description

Schweitzer Engineering Laboratories (SEL) in Burnaby, BC is seeking a Lead Engineer focused on VHDL RTL digital logic design to guide our R&D Communications product group. You will contribute to SONET/VSN multiplexers, Ethernet gateways, and network timing systems while mentoring teammates and shaping architecture.

This role requires hands-on RTL design for FPGAs, strong documentation, and collaboration with product managers to deliver safe, reliable, and economical electric power protection