Senior RTL/FPGA Design Eng - Verilog, Vivado, CDC (Contract)

LanceSoft, Inc.; Ottawa; On-site; CAD 151,536 - 185,976; Full time

Job summary

A leading semiconductor company is seeking an RTL/FPGA Design Engineer with over 15 years of experience. The ideal candidate should have a bachelor's degree in engineering or computer science and possess excellent skills in RTL design using Verilog and System Verilog. Key responsibilities include working with EDA tools and knowledge of networking standards. This contract position offers a pay range of CA$110.00/hr to CA$135.00/hr.

Qualifications

• At least 15 years of experience in digital ASIC/FPGA design.
• Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog.
• Knowledge of networking standards and wired communications protocols (such as Ethernet).

Skills

ASIC RTL Design

Clock Domain Crossing (CDC) Analysis

RTL Synthesis

Scripting languages (Python, Perl, TCL)

Vivado Design Suite

Education

Bachelor’s degree in engineering or computer science

Tools

Synopsys Design/Fusion Compiler

Synopsys VCS simulation

Vivado Design Suite

Job description

A leading semiconductor company is seeking an RTL/FPGA Design Engineer with over 15 years of experience. The ideal candidate should have a bachelor's degree in engineering or computer science and possess excellent skills in RTL design using Verilog and System Verilog. Key responsibilities include working with EDA tools and knowledge of networking standards. This contract position offers a pay range of CA$110.00/hr to CA$135.00/hr.