Digital Verification Engineer II — High-Impact IP

Cadence Design Systems; Montreal (administrative region); Hybrid; CAD 74,000 - 137,000; Full time

Benefits offered by this job

RRSP participation

TFSA/retirement savings

Life insurance

Health coverage with dental/vision

Stock Purchase Plan

Job summary

Cadence Design Systems is seeking a Design Engineer II to join a dynamic team in Montreal, Ottawa, and Toronto. The role focuses on verification of digital RTL and development of reusable verification environments within a high-performance IP context. Collaboration across design, verification, and project management teams across global sites is essential.

The candidate should have a B.S. in EE/CPE/CSC, strong SV/UVM knowledge, and experience with scripting (Python).

Qualifications

• Bachelor of Science in Electrical/Computer Engineering or Computer Science.
• Understanding of verification architecture and methodologies.
• Understanding of Metric Driven Verification and Universal Verification Methodologies.
• Knowledge of SystemVerilog Assertions (SVAs) and digital design flow.

Responsibilities

• Verify digital RTL and develop reusable verification components/environments.
• Contribute to verification flow development, test plan execution, and coverage closure.
• Communicate progress effectively with cross-functional teams across multiple geographies.
• Collaborate with design, verification, project management, and analog/digital design groups.

Skills

RTL verification

SV/UVM fundamentals

Python scripting

Communication skills

Education

Bachelor of Science in Electrical/Computer Engineering or Computer Science

Tools

Cadence tools

SystemVerilog

Job description

Cadence Design Systems is seeking a Design Engineer II to join a dynamic team in Montreal, Ottawa, and Toronto. The role focuses on verification of digital RTL and development of reusable verification environments within a high-performance IP context. Collaboration across design, verification, and project management teams across global sites is essential.

The candidate should have a B.S. in EE/CPE/CSC, strong SV/UVM knowledge, and experience with scripting (Python).