Senior/Process Engineer -Die Preparation

STATS CHIPPAC MANAGEMENT PTE. LTD.; Região Norte; Presencial; BRL 320 000 - 460 000; Tempo integral

Resumo da oferta

STATS CHIPPAC MANAGEMENT PTE. LTD. seeks a senior engineer to drive DP process development, optimization and baseline stabilization for advanced packaging.

You will lead wafer backgrinding, dicing and tape lamination, qualification, and SOP establishment, while mentoring a growing DP engineering team. The role emphasizes root-cause analysis, cross-functional collaboration with equipment and integration teams, and strong vendor management to scale DP operations in a high-tech semiconductor

Qualificações

• Degree in materials, chemical, mechanical, electrical/electronic engineering or related field required.
• 8–10 years in semiconductor process engineering with DP/MEOL or 2.5D/3D packaging experience.
• Hands-on experience with wafer backgrinding, dicing, tape lamination and die attach.
• Proven leadership of engineering teams and resource planning for line expansion.
• Strong DP baseline stabilization, recipe optimization and defect analysis skills.
• Experience with material and vendor management and cross-functional collaboration.

Responsabilidades

• Lead DP process development, optimization and baseline stabilization.
• Oversee wafer backgrinding, blade/laser dicing and tape lamination activities.
• Drive DP qualification, recipe management and SOP establishment.
• Improve yield via root-cause failure analysis and process margin improvements.
• Lead and mentor the DP engineering team and manage vendor relations.
• Coordinate cross-functional efforts with equipment and integration teams.

Conhecimentos

Team leadership

Root-cause analysis

Cross-functional collaboration

English communication

Process optimization

Formação académica

Bachelor's degree+

Ferramentas

Wafer backgrinding equipment

Blade/Laser dicing equipment

Tape lamination equipment

Die attach equipment

Descrição da oferta de emprego

Key Job Accountabilities:

• Die Preparation (DP) Process Development, Optimization & Baseline Stabilization
• Wafer Backgrinding, Blade/Laser Dicing & Pick-and-Place Process Control
• New DP Process Qualification, Recipe Management & SOP Establishment
• Yield Enhancement, Defect Reduction & Root-Cause Failure Analysis (FA)
• Advanced Packaging / Thin-Wafer Handling & Fine-Pitch Dicing Capability Setup
• Technical Leadership, Team Building & Mentoring for Expanding DP Engineering Team
• Material (Tapes, Blades, Chemicals) & Vendor Technical Management

Required Experience and Qualifications:

• Bachelor’s degree or higher in Materials Science, Chemical Engineering, Mechanical Engineering, Electrical/Electronic Engineering, or related disciplines
• R&D or mass production experience of at least 8 to 10 years in semiconductor process engineering, specifically in Die Preparation (DP), MEOL, or 2.5D/3D advanced packaging (CoW)
• Hands-on experience and deep process knowledge in unit operations: Wafer Backgrinding, Blade/Laser Dicing, Tape Lamination/Mounting, Die Attach, and Pick-and-Place
• Proven experience or strong potential in leading engineering teams, establishing new process flows, and allocating resources for expanding line operations
• In-depth technical capability in DP baseline process stabilization, recipe optimization, thin-wafer handling, and defect analysis (e.g., chipping, cracking, delamination, warpage control)
• Strong capability in raw material and vendor management, including qualification of dicing tapes, blades, and process consumables alongside equipment suppliers
• Excellent problem-solving skills in root-cause failure analysis (FA), process margin enhancement, yield optimization, and cross-functional collaboration with equipment and integration teams
• Proficiency in technical documentation and reading/writing/presenting in English for senior management and customer interactions