R&D Process Engineer (Die-to-Wafer)

STATS CHIPPAC MANAGEMENT PTE. LTD.; Região Norte; Sur place; BRL 120 000 - 180 000; Plein temps

Résumé du poste

STATS CHIPPAC MANAGEMENT PTE. LTD. in Brazil Norte is seeking a Process Engineer to develop, qualify, and optimize Die-to-Wafer (D2W) processes for advanced packaging applications, including Flipchip and Underfill, across development to NPI.

You will work hands-on with DOE, optimization, and characterization, using JMP, and help establish MES flows, recipes, and device information for R&D builds. A degree in engineering and 3–5 years in semiconductor process engineering are preferred; strong

Qualifications

• Bachelor's degree in Engineering or related field.
• 3–5 years of hands-on semiconductor process engineering experience preferred.
• Experience in Die-to-Wafer, Flip Chip, Underfill, die attach, or advanced packaging processes is an advantage.

Responsabilités

• Develop and qualify D2W processes, including Flipchip and Underfill, for advanced packaging applications.
• Perform hands‑on process setup, DOE, optimization, characterization, and CI using JMP.
• Support process and yield improvement to achieve robust and scalable manufacturing processes.
• Develop and review FMEA, OCAP and Control Plans to identify and mitigate process risks.
• Create and maintain MES process flows, recipes, process instructions, BOM, and device information for R&D builds.
• Support process monitoring and reporting to facilitate transition to NPI.
• Collaborate with NPI, Operations, Quality and Equipment teams for qualification and tech transfer.

Connaissances

Problem-solving

Analytical skills

Communication skills

Independent work

Formation

Bachelor's degree in Engineering (Mechanical, Materials, Electronics)

Description du poste

About the role

Develop, optimize, and qualify Die-to-Wafer (D2W) processes, including Flipchip and Underfill, for advanced semiconductor packaging applications. Support process readiness, yield improvement, process robustness, and customer-specific technical solutions from development through NPI. Establish and maintain R&D process flows, recipes, instructions, and device information in MES to support engineering and qualification builds.

Key responsibilities

• Develop and qualify D2W processes, including Flipchip and Underfill, for advanced packaging applications such as 2.5D, Fan-In, and Fan-Out

• Perform hands‑on process setup, DOE, optimization, characterization, and continuous improvement using statistical tools such as JMP

• Support process and yield improvement to achieve robust and scalable manufacturing processes

• Develop and review FMEA, OCAP and Control Plans to identify and mitigate process risks

• Create and maintain MES process flows, recipes, process instructions, BOM, and device information for R&D builds

• Support process monitoring and reporting, including staging-time and yield monitoring, to facilitate transition to NPI

• Collaborate with NPI, Operations, Quality and Equipment teams to support process qualification, technology transfer and manufacturing readiness

About you

• Bachelor's degree in Engineering (Mechanical, Materials, Electronics, or related disciplines)

• 3–5 years of hands‑on semiconductor process engineering experience preferred

• Experience in Die-to-Wafer, Flip Chip, Underfill, die attach, or advanced packaging processes is an advantage

• Strong problem-solving and analytical skills

• Good communication skills with the ability to work effectively with cross‑functional teams

• Ability to work independently and manage multiple engineering activities in a fast‑paced semiconductor environment

• Fresh Engineering Graduates with strong interest in semiconductor process development are welcome to apply