Staff Layout Design Engineer — DDR/HBM IP (7nm+)

Synopsys, Inc.; Elsene; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Health and financial benefits

Job summary

Synopsys, Inc. is seeking an experienced memory-IP layout engineer to lead the DDR and HBM PHY layout across 7nm and below, in FinFET and GAA processes.

You will own floorplanning, layout execution, and design reviews for analog/mixed-signal blocks within memory PHY subsystems, and collaborate across circuit design, verification, and product engineering teams. You will mentor junior engineers, drive EMIR, PERC, DFM checks and LEF generation, estimate effort, plan schedules, and ensure

Qualifications

• 5+ years of hands-on custom layout experience in analog or mixed-signal IP.

Responsibilities

• Lead layout for DDR and HBM PHY IP across 7nm and below in FinFET/GAA.
• Own floorplanning and layout execution for memory PHY subsystems.
• Drive layout quality with PERC, EMIR, DFM checks and LEF generation.
• Collaborate with circuit design, verification, and product teams to resolve layout issues.

Skills

Layout design

Layout matching

Mentorship

Cross-functional collaboration

Education

Electronics/ VLSI Engineering

Tools

PERC

EMIR

DFM checks

LEF generation

Job description

Synopsys, Inc. is seeking an experienced memory-IP layout engineer to lead the DDR and HBM PHY layout across 7nm and below, in FinFET and GAA processes.

You will own floorplanning, layout execution, and design reviews for analog/mixed-signal blocks within memory PHY subsystems, and collaborate across circuit design, verification, and product engineering teams. You will mentor junior engineers, drive EMIR, PERC, DFM checks and LEF generation, estimate effort, plan schedules, and ensure