Physical Design Engineer

Intellectual Capital Resources; Antwerpen; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

Intellectual Capital Resources in Antwerp is seeking a Physical Design Engineer to join our semiconductor R&D team. You will own the RTL-to-GDS backend flow for complex digital circuitry used in imaging technology, with hands-on implementation and back-end methodology development.

You will collaborate with analog and digital teams, optimize performance, power and area, and contribute to automation scripts and flows. A strong background in microelectronics and Cadence tools is required.

Qualifications

• Experience with the digital backend flow from RTL to GDS.
• Experience with industry-standard EDA tools.
• Proficiency in scripting languages (Tcl, Python).
• Experience with Cadence tools is preferred.
• CMOS image sensor architectures experience is highly desirable.

Responsabilités

• Execute the complete digital backend flow from RTL to GDS, including synthesis, floorplanning, power planning, place & route, clock tree synthesis (CTS), static timing analysis (STA) and logic equivalence checking (LEC)
• Provide innovative solutions to reach product targets and drive performance, power and area optimizations
• Develop, maintain and enhance backend methodologies, flows and automation scripts
• Collaborate closely with the analog team and the digital design and verification engineers to resolve implementation challenges and successfully complete the project
• Participate in design/architecture reviews and risk assessments from a physical implementation perspective

Connaissances

RTL to GDS flow

Scripting Tcl/Python

Cadence tools

EDA tools

CMOS image sensors

Formation

Bachelor’s degree in microelectronics

Outils

Cadence tools

EDA tools

Description du poste

This client is looking for a Physical Design Engineer to join their semiconductor R&D team in Antwerp, working on the implementation of complex digital circuitry for advanced imaging technologies.
This is a hands‑on Physical Design Engineer position covering the RTL-to-GDS flow, with scope to work across implementation, optimisation and backend methodology development.

Key responsibilities

• Execute the complete digital backend flow from RTL to GDS, including synthesis, floorplanning, power planning, place & route, clock tree synthesis (CTS), static timing analysis (STA) and logic equivalence checking (LEC)
• Provide innovative solutions to reach product targets and drive performance, power and area optimizations
• Develop, maintain and enhance backend methodologies, flows and automation scripts
• Collaborate closely with the analog team and the digital design and verification engineers to resolve implementation challenges and successfully complete the project
• Participate in design/architecture reviews and risk assessments from a physical implementation perspective

Position Qualifications

• Bachelor’s degree or above in microelectronics or related fields
• Experience with the complete digital backend flow from RTL to GDS
• Experience with industry-standard EDA tools
• Proficiency in scripting languages (Tcl, Python)
• Experience with Cadence tools is preferred
• Experience with CMOS image sensor architectures is highly desireable