Senior FPGA Validation & Integration Engineer (Hybrid)

microTECH Global Limited; Vlaams-Brabant; Hybrid; EUR 65,000 - 111,000; Full time

Job summary

microTECH Global LTD in Leuven, Belgium, seeks an experienced FPGA Validation Design Engineer for a 3-month contract, hybrid work arrangement (3 days onsite, 2 days remote). Start ASAP. Role focuses on adapting ASIC RTL for FPGA, managing the FPGA flow, synthesis, and timing closure on physical hardware.

The ideal candidate will have 5+ years in FPGA/ASIC semiconductor design, strong digital verification skills, and hands-on FPGA implementation experience, including SystemVerilog and UVM.

Qualifications

• 5+ years in FPGA, ASIC or semiconductor design engineering.
• Strong experience in digital design verification.
• Proficiency with SystemVerilog and UVM.
• Hands-on FPGA synthesis, place-and-route and timing closure.
• Experience verifying complete devices and CPU/processor designs.

Responsibilities

• Modify and adapt ASIC RTL designs for FPGA integration.
• Set up and manage the FPGA development and implementation flow.
• Perform FPGA database verification for implementation readiness.
• Carry out FPGA synthesis and place-and-route.
• Analyse timing reports, identify violations and achieve timing closure.
• Update timing constraints to meet performance targets.
• Load bitstreams onto FPGA boards and validate hardware.
• Debug and troubleshoot FPGA hardware issues.
• Conduct design verification and functional validation of devices.

Skills

SystemVerilog

UVM

FPGA design

ASIC RTL

Timing analysis

Debugging FPGA

Independent work

Job description

microTECH Global LTD in Leuven, Belgium, seeks an experienced FPGA Validation Design Engineer for a 3-month contract, hybrid work arrangement (3 days onsite, 2 days remote). Start ASAP. Role focuses on adapting ASIC RTL for FPGA, managing the FPGA flow, synthesis, and timing closure on physical hardware.

The ideal candidate will have 5+ years in FPGA/ASIC semiconductor design, strong digital verification skills, and hands-on FPGA implementation experience, including SystemVerilog and UVM.