Senior DFT Engineer - Relocation to Leuven

Imec; Luik; On-site; EUR 90,000 - 120,000; Full time

Job summary

IMEC in Leuven, Belgium is seeking a Senior DFT Engineer to drive design-for-test strategies for complex SOCs in a world-leading R&D environment. You will architect DFT solutions and coordinate requirements with project teams to assure testability and performance.

You will implement innovative DFT techniques on SOCs and sub-systems, define timing for DFT test modes, and work with boundary scan, MBIST, OCC/OPCG, and IJTAG standards. Relocation support is provided for international applicants.

Qualifications

• Five or more years of experience in DFT insertion and ATPG for SOCs.
• Hands-on experience with boundary scan, compression, MBIST/repair, OPCG/OCC.
• Strong knowledge of IEEE 1149.x and IJTAG standards.
• Experience defining/maintaining DFT flows in complex designs.
• Proficiency with Verilog/VHDL for test logic and TCL scripting.

Responsibilities

• Architect DFT solutions for SOCs with multiple sub-blocks and complex IPs.
• Coordinate/negotiate DFT requirements with project teams and customers.
• Implement and validate innovative DFT techniques on SOCs and subsystems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/repair, OCC for large-scale designs.
• Generate test patterns and improve fault coverage; support post-silicon test patterns.
• Collaborate with the physical design team on timing violations and signal integrity.
• Collaborate with the test engineering team on silicon characterization and validation.

Skills

DFT insertion and ATPG

Verilog/VHDL basics

DFT owner of sub-systems

DFT integration with PHY blocks

SDC constraints for DFT

Boundary scan, MBIST/repair, OPCG/OCC

IEEE 1149.1/1149.6/1687 (IJTAG)

EDA tools: Tessent, Genus/Modus

Tessent SSN

Scripting: TCL

Tools

Tessent (Siemens)

Genus/Modus (Cadence)

Simulation tools

Job description

IMEC in Leuven, Belgium is seeking a Senior DFT Engineer to drive design-for-test strategies for complex SOCs in a world-leading R&D environment. You will architect DFT solutions and coordinate requirements with project teams to assure testability and performance.

You will implement innovative DFT techniques on SOCs and sub-systems, define timing for DFT test modes, and work with boundary scan, MBIST, OCC/OPCG, and IJTAG standards. Relocation support is provided for international applicants.