Senior DFT Engineer – Lead SoC Testability, Leuven

IMEC; Belgique; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Relocation support

Job summary

IMEC is seeking a Senior DFT Engineer to shape next-gen semiconductors through advanced Design-for-Test innovation. You will lead SOC testability, ensure quality and performance of complex chip designs, and collaborate with multiple teams in a world-class R&D setting.

Based at Leuven/Belgium HQ, relocation support is available for international applicants. English proficiency required, with strong expertise in DFT, ATPG, IEEE IJTAG, and TCL scripting.

Qualifications

• DFT design and insertion experience for SOCs with complex IPs.
• Experience with ATPG and fault coverage improvement.
• Proficiency in Verilog/VHDL for test logic as needed.

Responsibilities

• Architect DFT solutions for SOCs with multiple sub-blocks and complex IPs.
• Coordinate DFT requirements with project teams and customers.
• Implement and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/repair, OPCG/OCC for large-scale designs.
• Generate test patterns, debug fault coverage, and support post-silicon test patterns.
• Collaborate with physical design on timing, signal/power integrity and routing.
• Collaborate with test engineering for silicon characterization and validation.
• 5+ years of experience with DFT insertion and ATPG.
• Basic Verilog/VHDL for test logic as needed.
• Experience with DFT integration of PCIe, UCIe, LPDDR5, etc.
• Define and verify DFT flows and standards (IEEE 1149.x, IJTAG).
• Scripting skills, especially TCL, for automation.

Skills

DFT insertion

ATPG

Verilog/VHDL

DFT ownership

IEEE IJTAG

TCL scripting

Chiplets DFT

Tools

Tessent (Siemens)

Genus/Modus (Cadence)

Tessent SSN

ICL/PDL file formats

Job description

IMEC is seeking a Senior DFT Engineer to shape next-gen semiconductors through advanced Design-for-Test innovation. You will lead SOC testability, ensure quality and performance of complex chip designs, and collaborate with multiple teams in a world-class R&D setting.

Based at Leuven/Belgium HQ, relocation support is available for international applicants. English proficiency required, with strong expertise in DFT, ATPG, IEEE IJTAG, and TCL scripting.