Senior DFT Engineer: Lead Testability for Next-Gen Chips

Imec; Vlaams-Brabant; Sur place; EUR 90 000 - 120 000; Plein temps

Avantages offerts par ce poste

Fringe benefits

Résumé du poste

IMEC in Leuven, Belgium seeks a Senior DFT Engineer to drive design-for-test for SOCs in cutting-edge semiconductor projects. You will architect DFT solutions, coordinate requirements with teams and customers, and implement innovative techniques across complex IP and large-scale designs.

Join a world-class R&D environment, collaborating with physical design and test engineering to validate silicon and optimize fault coverage.

Qualifications

• 5+ years of experience with DFT insertion and ATPG.
• Fluent in Verilog/VHDL to write test logic when needed.
• Experience as a DFT owner of sub-systems including insertion and verification of all DFT structures.
• Experience with DFT integration of complex PHY blocks (PCIe, UCIe, LPDDR5, etc.).
• Define SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, test debug.
• Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL).
• Preferably experience with defining/maintaining DFT flows.
• Experience with chiplet DFT (IEEE1838) is a plus.
• Scripting languages, especially TCL.

Responsabilités

• Architect DFT solutions for SOCs with multiple sub-blocks/partitions and complex IPs.
• Coordinate/Negotiate DFT requirements with project teams and customers.
• Implement and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/Repair, OPCG/OCC for large-scale designs in advanced nodes.
• Generate test patterns, debug fault coverage, support post-silicon test patterns, diagnose memory and scan issues.
• Work with physical design on timing violations, signal/power integrity, and routing congestion.
• Collaborate with test engineering on silicon characterization and validation.

Connaissances

DFT insertion

ATPG

Verilog/VHDL

DFT ownership

DFT integration

SDC constraints

Boundary scan

MBIST/repair

OPCG/OCC

Fault coverage

Test debugging

IJTAG

DFT flows

TCL scripting

IEEE1838

Outils

Tessent

Tessent SSN

Genus/Modus

Cadence

Description du poste

IMEC in Leuven, Belgium seeks a Senior DFT Engineer to drive design-for-test for SOCs in cutting-edge semiconductor projects. You will architect DFT solutions, coordinate requirements with teams and customers, and implement innovative techniques across complex IP and large-scale designs.

Join a world-class R&D environment, collaborating with physical design and test engineering to validate silicon and optimize fault coverage.