Senior DFT Engineer: SoC Test & Validation Leader

Imec India Private Limited; Heverlee; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

IMEC in Leuven, Belgium, seeks a Senior DFT Engineer to design and implement advanced test solutions for SOCs and multi-block chips in a world-leading R&D environment.

You will collaborate with physical design and test teams to define DFT flows, insert techniques, and validate fault coverage across 5nm+ nodes, leveraging state-of-the-art EDA tools and scripting. The role offers growth within a premier nanotechnology center.

Qualifications

• 5+ years of experience with DFT insertion and ATPG.

Responsabilités

• Architect DFT solutions for SOCs with multiple sub-blocks/partitions and complex soft/hard IPs with complex DFT requirements.
• Coordinate/Negotiate DFT requirements with the project teams and the customers.
• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/Repair, OCC for large-scale low-power designs in advanced nodes (5nm and beyond).
• Generate test patterns, debug/improve fault coverage, support debug of post-silicon test patterns, diagnose memory and scan issues.
• Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.
• Work closely with the test engineering team on silicon characterization and validation.

Connaissances

DFT insertion

ATPG

Verilog/VHDL

DFT ownership

DFT integration (PHY blocks)

SDC constraints

Boundary scan/Compression/MBIST/Repair

TCL scripting

DFT flows maintenance

IEEE IJTAG

DFT for chiplets

Scripting for test

Outils

Tessent (Siemens)

Genus/Modus (Cadence)

Simulation tools

Tessent SSN

IEEE1838 support

Description du poste

IMEC in Leuven, Belgium, seeks a Senior DFT Engineer to design and implement advanced test solutions for SOCs and multi-block chips in a world-leading R&D environment.

You will collaborate with physical design and test teams to define DFT flows, insert techniques, and validate fault coverage across 5nm+ nodes, leveraging state-of-the-art EDA tools and scripting. The role offers growth within a premier nanotechnology center.