Senior DFT Engineer: Pushing 5nm IC Test Innovation

EURAXESS Ireland; Belgique; À distance; EUR 90 000 - 130 000; Plein temps

Résumé du poste

imec, based in Leuven, Belgium, seeks a Senior DFT Engineer to advance design-for-test for next-generation semiconductors. You will develop test architectures and collaborate across IC teams to ensure high testability and performance of complex chip designs.

You will define DFT strategies, implement advanced techniques, and work with state-of-the-art EDA tools in a world-leading R&D environment. This role offers a competitive salary and fringe benefits.

Qualifications

• 5+ years of experience with DFT insertion and ATPG.
• Fluent in Verilog or VHDL for test logic.
• Experience as a DFT owner of sub-systems including DFT insertion/verification.
• Experience with DFT integration for complex PHY blocks (PCIe, UCIe, LPDDR5).
• Hands-on experience defining SDC constraints for DFT and related test debug tasks.
• IEEE 1149.1, 1149.6, 1687 (IJTAG) standards and formats (ICL, PDL).
• Scripting in TCL; experience with DFT flows and testbench automation.

Responsabilités

• Architect DFT solutions for SOCs with multiple sub-blocks and complex IPs.
• Coordinate DFT requirements with project teams and customers.
• Implement and validate innovative DFT techniques on SOCs and subsystems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/Repair, OCC for large designs.
• Generate test patterns and improve fault coverage; debug post-silicon tests.
• Collaborate with physical design on timing, signal/power integrity, and routing.

Connaissances

DFT Insertion

ATPG

Verilog/VHDL

Tessent

Genus/Modus

TCL Scripting

IJTAG

IEEE 1838

Outils

Tessent (Siemens)

Genus/Modus (Cadence)

Description du poste

imec, based in Leuven, Belgium, seeks a Senior DFT Engineer to advance design-for-test for next-generation semiconductors. You will develop test architectures and collaborate across IC teams to ensure high testability and performance of complex chip designs.

You will define DFT strategies, implement advanced techniques, and work with state-of-the-art EDA tools in a world-leading R&D environment. This role offers a competitive salary and fringe benefits.