Senior ASIC/SoC Verification Engineer (SystemVerilog/UVM)

DSJ Global; Vlaams-Brabant; On-site; EUR 70,000 - 95,000; Full time

Job summary

DSJ Global is partnering with an established semiconductor engineering organisation in Belgium to strengthen its ASIC/SoC verification capability. You will take ownership of verifying complex digital IP and ASIC/SoC designs, developing robust verification environments and ensuring designs meet functional requirements before implementation.

You will develop verification strategies, create SystemVerilog/UVM testbenches, and drive coverage through directed and constrained-random testing, while

Qualifications

• 5 to 10+ years in ASIC/SoC design verification.
• Expertise in SystemVerilog and UVM.
• Experience building verification environments and testbenches.
• Strong RTL debugging and coverage-driven verification.

Responsibilities

• Develop verification strategies and detailed verification plans from design and architectural specifications.
• Create and maintain SystemVerilog/UVM testbenches.
• Develop directed and constrained-random test cases.
• Build reusable verification components, sequences, monitors, scoreboards and assertions.
• Perform functional and code coverage analysis and drive verification towards coverage closure.
• Debug RTL and simulation failures alongside digital design engineers.

Skills

SystemVerilog

UVM

Constrained-random verification

Functional coverage

RTL debugging

Verilog/SystemVerilog RTL

Testbench development

Verification environments

Assertions and checkers

Job description

DSJ Global is partnering with an established semiconductor engineering organisation in Belgium to strengthen its ASIC/SoC verification capability. You will take ownership of verifying complex digital IP and ASIC/SoC designs, developing robust verification environments and ensuring designs meet functional requirements before implementation.

You will develop verification strategies, create SystemVerilog/UVM testbenches, and drive coverage through directed and constrained-random testing, while