[NanoIC topic] Admittance modeling for scoping defects in advanced germanium Metal-Oxide-Semiconductor gate stacks for CFET

Imec; Vlaams-Brabant; On-site; EUR 6,700 - 11,000; Full time

Benefits offered by this job

Imec allowance

Allowance for non-Belgian students

Job summary

imec in Belgium offers a Master or PhD internship to develop and implement an admittance model for CFET gate stacks using Comphy, focusing on fitting experimental data and refining the approach.

The project emphasizes physics-based modeling of defect populations, temperature effects and parasitic contributions, aiming for robust, physically meaningful extraction in collaboration with imec's advanced semiconductor teams.

Qualifications

• Master internship or PhD internship
• Strong modeling and data fitting skills preferred
• Background in semiconductor devices advantageous

Responsibilities

• Develop admittance model in Comphy and fit experimental data
• Apply physics-based defect modeling to extract energetic/kinetic properties
• Iteratively refine the model and fitting strategy for robust, meaningful parameters
• Collaborate with imec’s devices/materials/characterization teams

Education

Electrotechnics/Electrical Engineering

Nanoscience & Nanotechnology

Physics

Materials Engineering

Job description

[NanoIC topic] Admittance modeling for scoping defects in advanced germanium Metal-Oxide-Semiconductor gate stacks for CFET

Solve the characterization and modeling challenge enabling tomorrow’s CFET technology

CMOS scaling isentering the 3D era with complementary field-effect transistors (CFETs), inwhich n- and p-type devices are vertically stacked on top of eachother reducingthe standard-cell footprint and improving transistor density without relyingsolely on further lateral pitch reduction. Germanium (Ge) is particularlyattractive for the p-channel device because its high hole mobility can increasedrive current and energy efficiency, making Ge-based CFET integration apotential enabler of higher-performance, more compact logic. However, Ge gatestacks remain highly sensitive to interface states and border traps, which candegrade mobility, shift threshold voltage, increase variability, and compromisereliability, particularly Bias Temperature Instability (BTI). Physics-baseddefect modeling used to correctly interpret widely collected frequency- andtemperature-dependent admittance measurements vs. bias, is essential toidentify the relevant defect populations, extract their energetic and kineticproperties, link them to materials and processing, and guide the optimizationof robust germanium gate stacks for manufacturable CFET technology.

The first partof the internship will focus on developing an admittance model, implementing itin Comphy, our in-house device simulator, and using it to fit experimentaldata. The model can be introduced in stages of increasing complexity, startingfrom the essential physics and progressively incorporating parasitic andsecondary effects, including series resistance, defect-assistedminority-carrier generation, surface-potential fluctuations, and temperaturedependencies.

The second partof the internship will apply the model to real-world experimental datasets toevaluate whether the fitting approach performs reliably in practice. Based onthe observed agreement, stability, and parameter sensitivity, the model andfitting methodology will be iteratively refined, including the fittingstrategy, parameter constraints, and treatment of measurement artefacts, toachieve the most accurate, robust, and physically meaningful extractionpossible.

We offer aninterdisciplinary research environment that brings together world-leadingexpertise in semiconductor devices, materials, characterization, andphysics-based modeling. The intern will work in imec’s state-of-the-artlaboratory environment and gain exposure to research conducted in closecollaboration with the world’s leading semiconductor companies, providing aunique opportunity to contribute to technology developments with directindustrial relevance.

Type of internship: Master internship, PhD internship

Duration: minimum 6 months

Required educational background: Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics, Materials Engineering

Imec allowance will be provided for students studying at a non-Belgian university.

imec's cleanroom