Innovative FPGA Design Engineer – RTL, DSP, Xilinx (Antwerp)

Vivid Resourcing; Antwerpen; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

Vivid Resourcing is recruiting an FPGA Design Engineer in Antwerp, Belgium. You will join a highly technical R&D team responsible for the design, development and verification of FPGA-based solutions across the lifecycle from architecture through to timing, synthesis and debugging.

You will work with Xilinx toolchains and VHDL/Verilog to deliver efficient hardware architectures, optimize performance and collaborate with hardware and software engineers to ensure robust, reliable designs.

Qualifications

• Experience across the FPGA development lifecycle from architecture to verification.
• Proficient in VHDL or Verilog and able to translate system requirements into hardware designs.
• Strong knowledge of timing analysis and closure techniques.

Responsabilités

• Design and develop FPGA-based solutions for advanced semiconductor applications.
• Translate system requirements into efficient digital hardware architectures.
• Develop RTL designs using VHDL and/or Verilog.
• Perform simulation, verification and debugging of FPGA designs.
• Carry out synthesis, place & route and timing analysis.
• Analyse and optimise designs for performance, resource utilisation and reliability.
• Work with hardware and software engineers throughout the development lifecycle.
• Contribute to design documentation, testing and verification activities.
• Support the integration of FPGA solutions into wider electronic systems.
• Investigate and resolve complex technical issues.

Connaissances

FPGA Design

RTL design

Digital Logic & Digital Design

FPGA Simulation & Verification

Timing Analysis & Timing Closure

Outils

Xilinx

VHDL/Verilog

FPGA development tools

Description du poste

Vivid Resourcing is recruiting an FPGA Design Engineer in Antwerp, Belgium. You will join a highly technical R&D team responsible for the design, development and verification of FPGA-based solutions across the lifecycle from architecture through to timing, synthesis and debugging.

You will work with Xilinx toolchains and VHDL/Verilog to deliver efficient hardware architectures, optimize performance and collaborate with hardware and software engineers to ensure robust, reliable designs.