Aerospace ASIC Design Engineer – Digital RTL & Verification

Vivid Resourcing; Vlaams-Brabant; Sur place; EUR 60 000 - 90 000; Plein temps

Résumé du poste

Vivid Resourcing is recruiting an ASIC Design Engineer for an aerospace technology company based in Leuven, Belgium. You will join a highly technical R&D team working on the design, development and verification of advanced digital hardware across the ASIC lifecycle.

The role involves RTL/ASIC design, VHDL/Verilog, FPGA work, timing closure and collaboration with senior engineers. Proficiency in Python, MATLAB or SystemC and a good command of English are highly valued; Belgian work permit is

Qualifications

• Master’s degree or PhD in Electronics, Electrical Engineering, Computer Science, Applied Physics or a related discipline.
• Experience with ASIC, FPGA or digital hardware design.
• Good understanding of RTL design and digital logic.
• Experience with VHDL or Verilog.
• Programming experience, ideally with Python, MATLAB, SystemC or similar.
• Professional working proficiency in English.
• Belgian work permit.

Responsabilités

• Design and develop digital ASIC solutions.
• Create and maintain RTL designs.
• Develop, simulate and verify digital designs.
• Work through logic synthesis and timing closure.
• Analyse and resolve complex technical challenges.
• Use industry-standard EDA tools throughout the development process.
• Document designs and contribute to verification activities.
• Collaborate with technical leads and engineers across the wider R&D organisation.
• Contribute to the development and improvement of design methodologies.

Connaissances

ASIC / FPGA design

RTL design

VHDL / Verilog

English proficiency

Belgian work permit

Formation

Master’s degree or PhD in Electronics/EE/CS/Applied Physics

Outils

EDA tools

Git

MATLAB

Python

SystemC

Description du poste

Vivid Resourcing is recruiting an ASIC Design Engineer for an aerospace technology company based in Leuven, Belgium. You will join a highly technical R&D team working on the design, development and verification of advanced digital hardware across the ASIC lifecycle.

The role involves RTL/ASIC design, VHDL/Verilog, FPGA work, timing closure and collaboration with senior engineers. Proficiency in Python, MATLAB or SystemC and a good command of English are highly valued; Belgian work permit is