Exploring pinning mechanism for single-bit domain wall devices

Imec; Vlaams-Brabant; On-site; EUR 10,000 - 17,000; Full time

Job summary

Imec in Belgium invites PhD or Master internship applicants to explore pinning mechanisms for single-bit domain-wall devices, focusing on energy-efficient DW confinement in extended magnetic layers. The project combines nanoscale MTJ platforms, micromagnetic simulations, and CMOS-compatible integration.

You will perform simulations using OOMMF/MuMax, analyze DW dynamics under magnetic field and SOT, and contribute to publication-quality reports under the supervision of Van Dai Nguyen.

Qualifications

• Background in materials engineering, physics or nanoscience with strong fundamentals.
• Experience with micromagnetic simulations and related software is a plus.
• Interest in spintronics and memory technologies; self-mufficient for a PhD/Master internship.

Responsibilities

• Contribute to research on DW pinning and confinement strategies.
• Perform simulations and analyze DW dynamics under field- and SOT-driven motion.
• Collaborate with IMEC scientists and document findings.

Skills

Geometrical pinning concepts

Micromagnetic simulations

CMOS compatibility

Education

Materials Engineering

Physics

Nanoscience & Nanotechnology

Tools

OOMMF

MuMax

Job description

Exploring pinning mechanism for single-bit domain wall devices

Controlling domain walls for next-generation memory

The rapid growth of AI-driven applications today ispushing conventional charge-based memory technologies to their limits due tothe concerns in reliability, scalability, and volatility. This pushes apressing need for alternative memory solutions that offer faster operation,higher endurance, and non-volatile data storage.

Spintronics, which exploits electronspin in addition to charge, offers a promising pathway for next-generationmemory. Its combination of non-volatility, fast switching, and high integrationdensity makes Magnetic Random-Access Memory (MRAM) a strong candidate tocomplement or replace conventional charge-based memories across the memoryhierarchy.

MRAM uses Magnetic Tunnel Junctions(MTJs) to store and read information through the magnetic state and TunnellingMagnetoresistance (TMR). While STT-MRAM suffers from high switching currentsand reliability concerns, SOT-MRAM separates read and write paths for fasterswitching and improved endurance. However, switching the entire magnetic layerremains energy-intensive, and reliable field-free switching is still a majorchallenge.

Single-bit domain-wall (DW) devicesoffer an attractive alternative by encoding information in the position of a DWwithin an extended magnetic layer. Since only the DW needs to be displacedrather than the entire magnetic layer reversed, switching energy can besignificantly reduced. DW devices can also operate without an external magneticfield, making them promise scalable and energy-efficient memory.

At imec, we have demonstrated fullelectrical control of nanoscale DWs using MTJs on 300 mm wafer for both writingand reading, providing an important proof-of-concept for practical DWmanipulation at the nanoscale [1]. Building on this work, the project willinvestigate the physics of DW motion, with a particular focus on reliable DWconfinement near the MTJ. A key challenge is to control the position of DWwhile maintaining low-power operation. Because DWs can move easily under asmall driving current, excessive driving may cause DW to move beyond theintended storage region, leading to loss of information. This project willinvestigate different strategies to reliably confine the DW while maintaininglow-power operation and compatibility with CMOS-scalable devices.

This project explores geometricalpinning strategies to prevent DW annihilation and achieve reliable DWconfinement. The study will investigate the influence of geometrical design onDW dynamics under both magnetic field- and SOT-driven DW motion. Differentpinning geometries will be designed and systematically investigated usingmicromagnetic simulations with OOMMF and MuMax. The simulations will provideinsight into the underlying DW dynamics and the effectiveness of differentconfinement schemes, guiding the development of robust and low-power DW-basedmemory devices. The results will provide practical design guidelines foroptimizing geometrical pinning in future 1-bit DW-MRAM devices.

https://www.imec-int.com/en/articles/imec-brings-magnetic-domain-wall-devices-closer-industrial-reality

Type of internship: PhD internship, Master internship

Duration: 6 months to one year

Required educational background: Materials Engineering, Physics, Nanoscience & Nanotechnology

Supervising scientist(s): For further information or for application, please contact Van Dai Nguyen ( [e-mail] )

Only for self-supporting students.