[NanoIC topic] Pulsed Atomic Layer Etching for Next-Generation Spintronic memory and Quantum Devices

Imec; Vlaams-Brabant; On-site; EUR 12,000 - 16,000; Full time

Job summary

Imec invites applications for a Master internship (1 year) in the field of Pulsed Atomic Layer Etching for next-generation spintronic memory and quantum devices. The project targets low-damage ALE with strong patterning control on SOT-MRAM and quantum gate stacks.

The role emphasizes patterning accuracy, damage mitigation and advanced material characterization using techniques like ToF-SIMS, XPS, AFM and TEM.

Qualifications

• Master internship position in a relevant scientific field.
• Educational background spans chemistry, chemical engineering, materials science, energy or physics.
• University promoter: Stefan De Gendt (KU Leuven).

Responsibilities

• Investigate and optimize P ALE processes for patterning SOT MRAM and quantum gate stacks.
• Focus on process control, selectivity and damage mitigation.
• Collaborate with supervising scientist(s) and publish findings within the project.

Education

Chemistry/Chemical Engineering

Electrotechnics/Electrical Engineering

Materials Engineering

Energy

Nanoscience & Nanotechnology

Physics

Other

Tools

ToF-SIMS

XPS

AFM

TEM

EDS

Ellipsometry

XRD

Job description

/ [NanoIC topic] Pulsed Atomic Layer Etching for Next-Generation Spintronic memory and Quantum Devices

/ [NanoIC topic] Pulsed Atomic Layer Etching for Next-Generation Spintronic memory and Quantum Devices

Unified low-damage ALE framework for precise etch control in spintronic and quantum devices.

Simultaneously, there is a growing interest in quantum information technologies which has driven the exploration of scalable and design-flexible device architectures. Among these, 2D single-gate structures built on spin-on quantum-confined (Spin QC) substrates offer a promising path forward due to their straightforward layout and ease of extension to multi-qubit systems. H owever, the fabrication of high-fidelity gate profiles at critical gap dimensions remains a challenge , and minor deviations in etch landing might damage the gate oxide and modify the Spin QC interface which can directly degrade quantum device performance.

Conventional etch processes often introduce uncontrolled ion induced damage, roughness, and non-selectivity , which are detrimental to SOT efficiency , SOT switching reliability in spintronic devices, and integrity of bits in quantum technologies . P ulsed Atomic Layer Etching ( P ALE) offers a promising pathway to achieve highly controlled, low damage etching through cyclic and self-limited surface reactions.

This project aims to investigate and optimize P ALE processes for patterning SOT MRAM device and quantum gate stacks , focusing on process control, selectivity, and damage mitigation for advanced spintronic and quantum device integration. While the applications are different, the etch challenges remain similar and are therefore being addressed under the same topic.

The reliability and performance of both these devices critically depend on the etch process quality, especially with respect to:

Common Challenges for both Spintronic and Quantum devices -

• Mitigating residue formation post etch.

• Establishing the ALE window both in the adsorption and desorption steps .

• Ensuring sub nanometer scale sur fa ce modification and etch using material characterization techniques li k e Tof -SIMS, XPS, AFM, TEM, EDS, Ellipsometry , XRD, etc .

Challenges specific to spintronic device -

• Minimizing etch induced damage and modification of magnetic layers through crystalline damage and etchant diffusion.

• Achieving smooth sidewalls with low sidewall redeposition.

Challenges specific to Quantum device -

• Achieving precise landing control on the quantum gate oxide during gate patterning.

• Reducing the spacing between the quantum gates for efficient dot-to-dot coupling

Type of internship: Master internship

Duration: 1 year

Required educational background: Chemistry/Chemical Engineering, Electrotechnics/Electrical Engineering, Materials Engineering, Energy, Nanoscience & Nanotechnology, Physics, Other

Supervising scientist(s): For further information or for application, please contact Nikita Paul ( [e-mail] )

The reference code for this position is 2026-INT-200. Mention this reference code in your application.

Applications should include the following information:

• resume
• motivation
• current study

As spintronic devices such as z - spin Spin– O rbit T orque M agnetic R andom- A ccess M emory (SOT-MRAM) emerge as promising candidates for next generation embedded memory in high performance computing , etching of complex alloys including magnetic stacks become a critical process challenge. These devices require nanometer scale control of etch depth, profile, and material selectivity to preserve magnetic properties and device performance.

Simultaneously, there is a growing interest in quantum information technologies which has driven the exploration of scalable and design-flexible device architectures. Among these, 2D single-gate structures built on spin-on quantum-confined (Spin QC) substrates offer a promising path forward due to their straightforward layout and ease of extension to multi-qubit systems. H owever, the fabrication of high-fidelity gate profiles at critical gap dimensions remains a challenge , and minor deviations in etch landing might damage the gate oxide and modify the Spin QC interface which can directly degrade quantum device performance.

Conventional etch processes often introduce uncontrolled ion induced damage, roughness, and non-selectivity , which are detrimental to SOT efficiency , SOT switching reliability in spintronic devices, and integrity of bits in quantum technologies . P ulsed Atomic Layer Etching ( P ALE) offers a promising pathway to achieve highly controlled, low damage etching through cyclic and self-limited surface reactions.

This project aims to investigate and optimize P ALE processes for patterning SOT MRAM device and quantum gate stacks , focusing on process control, selectivity, and damage mitigation for advanced spintronic and quantum device integration. While the applications are different, the etch challenges remain similar and are therefore being addressed under the same topic.

The reliability and performance of both these devices critically depend on the etch process quality, especially with respect to:

Common Challenges for both Spintronic and Quantum devices -

• Mitigating residue formation post etch.

• Establishing the ALE window both in the adsorption and desorption steps .

• Ensuring sub nanometer scale sur fa ce modification and etch using material characterization techniques li k e Tof -SIMS, XPS, AFM, TEM, EDS, Ellipsometry , XRD, etc .

Challenges specific to spintronic device -

• Minimizing etch induced damage and modification of magnetic layers through crystalline damage and etchant diffusion.

• Achieving smooth sidewalls with low sidewall redeposition.

Challenges specific to Quantum device -

• Achieving precise landing control on the quantum gate oxide during gate patterning.

• Reducing the spacing between the quantum gates for efficient dot-to-dot coupling

Type of internship: Master internship

Duration: 1 year

Required educational background: Chemistry/Chemical Engineering, Electrotechnics/Electrical Engineering, Materials Engineering, Energy, Nanoscience & Nanotechnology, Physics, Other

University promotor: Stefan De Gendt (KU Leuven)

Supervising scientist(s): For further information or for application, please contact Nikita Paul ( [e-mail] )

The reference code for this position is 2026-INT-200. Mention this reference code in your application.

Applications should include the following information:

• resume
• motivation
• current study

Incomplete applications will not be considered.

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