Senior Mixed-Signal IC Design Engineer: Clocking Architect

Insight Global; Redmond; On-site; AUD 120,000 - 160,000; Full time

Job summary

Insight Global is seeking an accomplished Electrical Engineer to design and optimize DLLs and clock architectures for high-performance ICs. You will work on delay lines, phase alignment, clock conditioning, and deskew circuits, collaborating with layout and digital teams to ensure robust timing and low jitter.

The role requires expertise in analog/mixed-signal design, extensive clocking knowledge, and proficiency with Cadence Virtuoso.

Qualifications

• BS, MS, or PhD in Electrical Engineering.
• 5+ years of experience in analog or mixed-signal IC design.
• Strong experience designing DLLs, delay lines, phase alignment circuits, clock conditioning circuits.
• Deep understanding of clock generation and distribution architectures.
• Experience with Cadence Virtuoso and industry-standard simulation tools.

Responsibilities

• Design and develop Delay Locked Loops (DLLs) for high-performance clock generation and synchronization.
• Architect and optimize programmable delay lines and delay blocks for precise timing control.
• Develop clock distribution solutions including clock trees, buffers, dividers, and deskew circuits.
• Validate silicon performance through lab characterization and clock integrity measurements.
• Collaborate with layout engineers to minimize clock path mismatch and parasitics.

Skills

DLL design/implementation

Analog/mixed-signal IC design

Clock generation & distribution

Jitter analysis

Timing optimization

CMOS process knowledge

Circuit timing closure

Education

Electrical Engineering (BS/MS/PhD)

Tools

Cadence Virtuoso

Job description

Insight Global is seeking an accomplished Electrical Engineer to design and optimize DLLs and clock architectures for high-performance ICs. You will work on delay lines, phase alignment, clock conditioning, and deskew circuits, collaborating with layout and digital teams to ensure robust timing and low jitter.

The role requires expertise in analog/mixed-signal design, extensive clocking knowledge, and proficiency with Cadence Virtuoso.