Senior Mixed-Signal IC Design Engineer – DLL, Delay Line & Clocking Architectures

Insight Global; Redmond; On-site; AUD 120,000 - 160,000; Full time

Job summary

Insight Global is seeking an accomplished Electrical Engineer to design and optimize DLLs and clock architectures for high-performance ICs. You will work on delay lines, phase alignment, clock conditioning, and deskew circuits, collaborating with layout and digital teams to ensure robust timing and low jitter.

The role requires expertise in analog/mixed-signal design, extensive clocking knowledge, and proficiency with Cadence Virtuoso.

Qualifications

• BS, MS, or PhD in Electrical Engineering.
• 5+ years of experience in analog or mixed-signal IC design.
• Strong experience designing DLLs, delay lines, phase alignment circuits, clock conditioning circuits.
• Deep understanding of clock generation and distribution architectures.
• Experience with Cadence Virtuoso and industry-standard simulation tools.

Responsibilities

• Design and develop Delay Locked Loops (DLLs) for high-performance clock generation and synchronization.
• Architect and optimize programmable delay lines and delay blocks for precise timing control.
• Develop clock distribution solutions including clock trees, buffers, dividers, and deskew circuits.
• Validate silicon performance through lab characterization and clock integrity measurements.
• Collaborate with layout engineers to minimize clock path mismatch and parasitics.

Skills

DLL design/implementation

Analog/mixed-signal IC design

Clock generation & distribution

Jitter analysis

Timing optimization

CMOS process knowledge

Circuit timing closure

Education

Electrical Engineering (BS/MS/PhD)

Tools

Cadence Virtuoso

Job description

Job Description

• Design and develop Delay Locked Loops (DLLs) for high-performance clock generation, synchronization, and phase alignment.
• Architect and optimize programmable delay lines and delay blocks for precise timing control.
• Develop clock distribution solutions including:Clock treesClock buffersClock dividersClock deskew circuitsDuty-cycle correction circuitsDesign and analyze DLL phase detectors, phase interpolators, charge pumps, and loop control circuitry.
• Perform extensive jitter analysis, including:Random jitterDeterministic jitterSupply-induced jitterClock uncertaintyPhase noise contributions
• Optimize clocking architectures for low skew, low power, and high timing accuracy.
• Analyze delay-line performance across PVT corners and process variations.
• Develop timing closure strategies with digital implementation and physical design teams.
• Support clock architecture development for high-speed mixed-signal and data converter systems.
• Collaborate with layout engineers to minimize clock path mismatch and parasitic effects.
• Validate silicon performance through lab characterization and clock integrity measurements.

Skills and Requirements

• BS, MS, or PhD in Electrical Engineering.
• 5+ years of experience in analog or mixed-signal IC design.
• Strong experience designing:DLLs (Delay Locked Loops)Delay linesPhase alignment circuitsClock conditioning circuitsDeep understanding of clock generation and distribution architectures.
• Experience with:Clock tree designClock deskew techniquesPhase detection circuitsTiming recovery systemsStrong knowledge of:Jitter analysisPhase noiseTiming uncertaintySkew optimizationLoop stabilityExperience with transistor-level design in advanced CMOS technologies.
• Proficiency with Cadence Virtuoso and industry-standard simulation tools.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [e-mail].