Senior DFT Engineer

IC Resources Recruitment; Town of Cambridge; On-site; AUD 114,481 - 171,722; Full time

Job summary

IC Resources Recruitment seeks a Senior DFT Engineer to join our ASIC team in Cambridge, England. You will design, implement and verify DFT solutions across the silicon flow, focusing on test coverage, cost, and time-to-market.

Day-to-day you will apply Tessent DFT tool flows for MBIST, EDT, SSN, IJTAG controls and IP test using ICL/PDL, verify structures, and resolve timing and UPF issues in a collaborative, fast-paced environment.

Qualifications

• 5+ years of industry experience in DFT engineering.
• Proven experience with IC development flows.
• Hands-on ATPG, MBIST, and simulation debugging.
• Proficiency with TCL scripting.

Responsibilities

• Define and implement DFT strategies at the chip, subsystem, and IP levels, balancing structural and functional methods while making pragmatic trade-offs.
• Utilize Tessent DFT tool flows for inserting MBIST, EDT, SSN, scan controls via IJTAG, and IP test using ICL/PDL in both flat and hierarchical designs.
• Verify DFT structures and debug related issues to ensure robust design implementation.
• Support DFT processes through implementation and sign-off, including generating timing constraints and resolving timing, power, and formal equivalence issues.

Skills

DFT

Tessent

MBIST

ATPG

IJTAG

IP test

UPF debugging

TCL scripting

IC flows

Verification

Education

Electronic engineering degree

Computer science degree

Tools

Tessent DFT tools

Job description

Senior DFT Engineer Overview

We are looking for a highly skilled and motivated Senior DFT (Design for Test) Engineer to join our expanding ASIC team in Cambridgeshire, England. This role presents an exciting opportunity to contribute to the development of next-generation products within a dynamic and collaborative environment. The ASIC team is responsible for overseeing the entire silicon flow, from specification and design to verification, implementation, ATE testing, and qualification.

As a member of a small and versatile team, you will engage in all aspects of delivering successful products to production. Your primary responsibilities will include creating, implementing, and verifying DFT solutions for future ASIC designs, ensuring that quality standards are maintained for products that are shipped in volume. You will leverage advanced DFT methodologies to optimize test coverage, cost, and time-to-market.

Responsibilities:

• Define and implement DFT strategies at the chip, subsystem, and IP levels, balancing structural and functional methods while making pragmatic trade-offs.
• Utilize Tessent DFT tool flows for inserting MBIST, EDT, SSN, scan controls via IJTAG, and IP test using ICL/PDL in both flat and hierarchical designs.
• Verify DFT structures and debug related issues to ensure robust design implementation.
• Support DFT processes through implementation and sign-off, including generating timing constraints and resolving timing, power, and formal equivalence issues.

Qualifications:

• A degree in electronic engineering, computer science, or a related discipline.
• At least 5 years of industry experience in DFT Engineering.
• Proven experience with IC development flows.
• Proficiency with Tessent DFT tools.
• Strong understanding of complex IP issues related to DFT, including on-chip clocking.
• Hands-on experience in ATPG, MBIST, and simulation debugging, including UPF-related issues.
• Proficiency in scripting, particularly TCL.

Degree Requirement: Bachelor’s

Visa Sponsorship May be