Senior Staff IC Layout Engineer (d/m/f)

ams-OSRAM AG; Oberpremstätten; On-site; EUR 70,000 - 110,000; Full time

Job summary

ams OSRAM's LSP unit seeks a senior IC layout engineer to design analog sensors and mixed-signal blocks, ensuring compliance with electrical and manufacturing rules.

You will optimize layout for SI/PI/HF, verify with LVS/DRC/DFM/ERC and collaborate across IP development and chip-package-board co-design. Proficiency with Cadence Virtuoso, PVS and Calibre is required; Synopsys tools are a plus.

Qualifications

• Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or a related field
• Minimum of 6 years experience in Semiconductor/Electronic Industry
• Strong experience with Cadence Virtuoso Suite (Virtuoso, PVS, Quantus)
• Experience with Cadence Virtuoso Suite and Physical Verification Tools such as Siemens Calibre/Cadence PVS is a must. Experience with Synopsys IC Custom Compiler and IC Validator is a clear benefit
• Knowledge of semiconductor processes, analog/mixed-signal design considerations, and ESD/EMC concepts is considered a strong benefit
• Knowledge of controlled impedance routing, electromagnetic coupling, grounding strategies, shielding concepts, and RF matching networks
• Experience with IC package substrates, wirebond and flip-chip packaging is beneficial
• CMOS IC layout experience, providing valuable expertise in parasitic control, matching techniques, device placement, shielding concepts, and chip-package-board co-design
• Good technical English is a must, German is beneficial

Responsibilities

• Design and develop IC layouts for analog sensors, and mixed-signal applications, ensuring compliance with electrical and manufacturing requirements
• Perform HF-aware component placement and routing, including controlled impedance structures, differential pairs, waveguides, and digital photonic implementations
• Optimize layout for signal integrity (SI), power integrity (PI), and HF performance, minimizing coupling, crosstalk, insertion loss, return loss, and electromagnetic interference (EMI)
• Create and verify IC layouts using Cadence Virtuoso Suite, Cadence PVS and Siemens Calibre
• Collaborate with IC analog design and package engineers to support IP development as well as chip-package-board co-design and ensure successful integration of high-precision circuits and support for simulation activities using SI/PI/EM extraction tools
• Perform design verification and manufacturability reviews, including LVS/DRC/DFM/ERC checks, fabrication rule compliance and parasitic extractions

Job description

We are LSP - Light Sensors & Photonics, one of three business units within ams OSRAM, advancing the digitalization of light. At LSP, we go beyond traditional sensing - combining light, silicon, and system expertise to enable digital photonics solutions. Our focus is clear: powering next-generation applications in data centers, AR/VR, mobile and automotive, where light becomes a critical interface for data, perception, and interaction. This evolution marks a shift from components to integrated photonics systems -driving performance, scalability, and innovation in high-growth segments.

• Design and develop IC layouts for analog sensors, and mixed-signal applications, ensuring compliance with electrical and manufacturing requirements
• Perform HF-aware component placement and routing, including controlled impedance structures, differential pairs, waveguides, and digital photonic implementations
• Optimize layout for signal integrity (SI), power integrity (PI), and HF performance, minimizing coupling, crosstalk, insertion loss, return loss, and electromagnetic interference (EMI)
• Create and verify IC layouts using Cadence Virtuoso Suite, Cadence PVS and Siemens Calibre
• Collaborate with IC analog design and package engineers to support IP development as well as chip-package-board co-design and ensure successful integration of high-precision circuits and support for simulation activities using SI/PI/EM extraction tools
• Perform design verification and manufacturability reviews, including LVS/DRC/DFM/ERC checks, fabrication rule compliance and parasitic extractions

• Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or a related field
• Minimum of 6 years experience in Semiconductor/Electronic Industry
• Strong experience with Cadence Virtuoso Suite (Virtuoso, PVS, Quantus)
• Experience with Cadence Virtuoso Suite and Physical Verification Tools such as Siemens Calibre/Cadence PVS is a must. Experience with Synopsys IC Custom Compiler and IC Validator is a clear benefit
• Knowledge of semiconductor processes, analog/mixed-signal design considerations, and ESD/EMC concepts is considered a strong benefit
• Knowledge of controlled impedance routing, electromagnetic coupling, grounding strategies, shielding concepts, and RF matching networks
• Experience with IC package substrates, wirebond and flip-chip packaging is beneficial
• CMOS IC layout experience, providing valuable expertise in parasitic control, matching techniques, device placement, shielding concepts, and chip-package-board co-design
• Good technical English is a must, German is beneficial

We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group G (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). We offer a higher compensation depending on your expertise and skills.