Senior FPGA Developer

Remotedxb; Dubai; On-site; AED 300,000 - 460,000; Full time

Job summary

Luxoft in Dubai is seeking an expert FPGA Architect to own end-to-end FPGA development for state-of-the-art communications products. You will drive architecture, IP selection, timing closure, and DFX while mentoring a team of FPGA engineers.

Qualifications include a BS/MS in Electrical/Computer Engineering and 12–15 years of relevant experience, with deep HDL expertise and track record in multi-Gbps SerDes/transceiver designs. Fluency in English is required.

Qualifications

• Bachelor or Master in Electrical or Computer Engineering with strong HDL background.
• Proven experience in architecting and delivering multi-Gbps FPGA designs.
• Experience with high-speed serial interfaces and Ethernet link-layer debugging.

Responsibilities

• Own FPGA architecture for state-of-the-art communications products.
• Define end-to-end FPGA architecture and IP make/buy tradeoffs.
• Oversee floorplanning and timing closure for multi-Gbps designs.
• Implement DFX approaches using HDL languages.
• Serve as escalation point for FPGA design and debugging issues.
• Mentor fellow FPGA engineers and drive root-cause analysis.
• Lead silicon/board bring-up debugging and issue resolution.

Skills

FPGA architecture

Verilog/SystemVerilog/VHDL

Timing closure

DFX for FPGA

High-speed transceivers

Hard IP & PLLs

Verifications (UVM/Cocotb)

Git/version control

Debugging silicon/board bring-up

PCIe & multi-Gbps design

Open verification methodologies

AI-assisted design tools

Education

BS or MS in Electrical or Computer Engineering

Tools

AMD/Altera FPGA toolchains

Siemens Questa

Aldec Riviera

Open verification flow (cocotb)

Job description

Responsibilities

• Own FPGA architecture for state-of-the-art Communications Test & Measurement products
• Define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP
• Manage floorplanning and timing closure strategy for multi-gigabit designs
• Implement DFX approach using Verilog, SystemVerilog, or VHDL
• Serve as the final technical escalation point for FPGA design and debug issues
• Mentor other FPGA engineers
• Lead root-cause debug of silicon and board bring-up issues

Requirements

• BS or MS degree in Electrical or Computer Engineering
• 12-15 years of relevant experience
• 5+ years architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs
• Expertise in high-speed FPGA designs using Verilog, SystemVerilog, or VHDL
• Hands-on expertise with FPGA transceivers, hard IP, and PLLs
• Experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T)
• Experience with optical interfaces and modules (SFPs, QSFPs)
• Knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP
• Extensive experience with AMD or Altera FPGA devices and toolchains
• Experience with formal verification or UVM-based verification methodologies
• Proven track record of taking FPGA designs from architecture to volume production
• Proficiency with Git or similar version control tools
• English fluency (B2 Upper Intermediate or higher)

Preferred Qualifications

• Patents or published work in FPGA architecture, high-speed digital design, or DSP
• Experience defining test strategies for multi-Gbps compliance testing
• Experience with microprocessor/DSP systems, PCIe, and high-speed digital board design
• Simulation experience using Siemens Questa or Aldec Riviera
• Familiarity with open verification methodologies like cocotb
• Utilization of generative AI tools for FPGA design implementation

About the Company

Luxoft is a global provider of software and engineering services, working on high-impact projects across various industries including telecommunications, cloud, and aerospace.