Lead RTL Architect for AI ASICs

Evollabs; Dubai; On-site; AED 350,000 - 550,000; Full time

Job summary

Evollabs in Dubai is seeking an experienced RTL/ASIC design engineer to own end-to-end subsystems from PLLs to interconnects. You will write production RTL, perform architecture trade-offs, and drive timing and verification for AI accelerator silicon.

The role requires hands-on experience across the chip development flow, from IP integration to pre-/post-silicon validation, with a focus on high-speed interfaces like PCIe/UCIe and memory bandwidth optimization.

Qualifications

• 7+ years of RTL design and ASIC development
• Experience with multi-core CPUs, NOCs, or high-speed interfaces like PCIe/UCIe
• Experience with AMBA protocols (AXI/AHB/APB) and CDC/RDC analysis

Responsibilities

• Own end-to-end design of ASIC subsystems from PLLs to interconnects
• Write production-quality RTL and perform integration/verification planning
• Define interfaces and perform architecture trade-offs for performance, power, and area
• Develop constraints, perform timing analysis and CTS with PD
• Simulate and verify at block and subsystem levels (UVM/formal)
• Document specifications, interfaces, and user guides

Skills

RTL design

Verilog/SystemVerilog

ASIC development

UVM

IP evaluation/selection

DFT/DFD

Timing closure

PPA optimization

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Primetime

EDA toolchain

SDC

Job description

Evollabs in Dubai is seeking an experienced RTL/ASIC design engineer to own end-to-end subsystems from PLLs to interconnects. You will write production RTL, perform architecture trade-offs, and drive timing and verification for AI accelerator silicon.

The role requires hands-on experience across the chip development flow, from IP integration to pre-/post-silicon validation, with a focus on high-speed interfaces like PCIe/UCIe and memory bandwidth optimization.