Senior ASIC Verification Architect – Dubai

Evollabs; Dubai; On-site; AED 350,000 - 550,000; Full time

Job summary

Evollabs in Dubai is seeking an ASIC Verification Engineer to own end-to-end verification for critical ASIC subsystems, from compute pipelines to high-speed I/O. You will architect UVM environments, drive coverage, and tie in emulation/FPGA with SW-in-the-loop to catch bugs before tape-out.

You will collaborate with silicon architects, RTL, firmware, and EDA to ensure first-pass silicon success, with strong emphasis on constrained-random stimulus, SVA, and formal methods.

Qualifications

• 7+ years in ASIC/SoC verification with SystemVerilog/UVM ownership from test plan to sign-off.
• Strong command of constrained-random stimulus, scoreboarding, coverage-driven verification, and SVA.
• Hands-on with major simulators and regression/CI tooling.

Responsibilities

• Own block-to-subsystem verification: author verification plans from specs and deliver sign-off with data coverage.
• Build scalable UVM environments: agents, monitors, scoreboards, sequences, reference models (C++/Python/DPI).
• Exercise real workloads: co-sim with firmware/drivers, run emulation/FPGA prototypes, correlate with models.
• Apply assertions & formal: write SVA, run formal where appropriate, integrate results into coverage.
• Harden regressions: own CI pipelines, randomized tests, triage failures, root-cause with RTL/design.
• Interface & document: keep specs, test plans, dashboards, and bug reports clear for all teams.

Skills

SystemVerilog/UVM

Constrained-random stimulus

Scoreboarding

Coverage-driven verification

SVA

Python scripting

AMBA/AXI/APB/AHB protocols

CI/Regression tooling

Tools

VCS

Questa

Xcelium

DPI (C++/Python)

Job description

Evollabs in Dubai is seeking an ASIC Verification Engineer to own end-to-end verification for critical ASIC subsystems, from compute pipelines to high-speed I/O. You will architect UVM environments, drive coverage, and tie in emulation/FPGA with SW-in-the-loop to catch bugs before tape-out.

You will collaborate with silicon architects, RTL, firmware, and EDA to ensure first-pass silicon success, with strong emphasis on constrained-random stimulus, SVA, and formal methods.