Wireless SoC Design Lead — Low Power & IP Integration

Apple Inc.; Cupertino (CA); On-site; USD 185,000 - 309,000; Full time

Benefits offered by this job

Employee stock programs

Discretionary bonuses

Relocation assistance

Medical and dental coverage

Job summary

Apple Inc. in Cupertino seeks a senior engineer to design CPU-based subsystems for high-performance, low-power wireless SoCs.

You will collaborate with SoC architects and IP developers to meet power, performance, and area goals while integrating IPs for Apple devices. You will engage in hardware/software/power partitioning discussions with cross-functional teams and write micro-architecture specifications, verifying RTL using SystemVerilog and industry tools.

Qualifications

• BS with 10+ years relevant experience.
• Familiarity with the ASIC design flow.
• Knowledge of digital design, SoC architecture, and HDL languages like Verilog.

Responsibilities

• Writing micro-architecture and design specifications.
• Coding design in SystemVerilog following established design guidelines, owning all aspects of RTL development design.
• Integrate IP blocks and optimize memories/hard macros required for the block.
• Supporting verification efforts at multiple levels.
• Checking your design with industry standard static tools such as LINT, CDC, RDC.
• Analyzing and optimizing area, timing, and power.
• Collaborate with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.

Skills

ASIC design flow

Digital design

SoC architecture

Verilog HDL

Education

BS in Electrical Engineering or related field

Tools

SystemVerilog

EDA tools

Job description

Apple Inc. in Cupertino seeks a senior engineer to design CPU-based subsystems for high-performance, low-power wireless SoCs.

You will collaborate with SoC architects and IP developers to meet power, performance, and area goals while integrating IPs for Apple devices. You will engage in hardware/software/power partitioning discussions with cross-functional teams and write micro-architecture specifications, verifying RTL using SystemVerilog and industry tools.