Senior Wireless MAC Design Engineer – Low-Power SoCs

Apple Inc.; Sunnyvale (CA); On-site; USD 184,700 - 324,800; Full time

Job summary

Apple Inc. is seeking a senior RTL design engineer to develop the MAC layer for wireless SoCs. You will translate system requirements into scalable microarchitecture and write area- and power-efficient RTL while collaborating with systems, verification, and synthesis teams.

Base pay ranges from $184,700 to $324,800, reflecting skills, experience, and location; Apple offers comprehensive benefits, employee stock programs, relocation support, and ongoing education reimbursement.

Qualifications

• BS in Electrical or Computer Engineering and 10+ years of relevant industry experience.
• Experience translating functional requirements into synthesizable Verilog or SystemVerilog RTL.
• Knowledge of RTL simulation, synthesis, lint, STA, and LEC; ability to design multi-clock-domain logic.

Responsibilities

• Prepare microarchitecture and RTL for wireless MAC based on functional requirements.
• Ensure lint, CDC, RDC cleanliness, and collaborate with the synthesis team on timing closure.
• Support verification/prototyping/emulation teams during pre-silicon verification, prototyping, and SW/FW development.
• Support post-silicon validation, system integration, and silicon design revisions.

Skills

Verilog

SystemVerilog

RTL design

CDC/STA/LEC

Education

BS in Electrical/Computer Engineering

Job description

Apple Inc. is seeking a senior RTL design engineer to develop the MAC layer for wireless SoCs. You will translate system requirements into scalable microarchitecture and write area- and power-efficient RTL while collaborating with systems, verification, and synthesis teams.

Base pay ranges from $184,700 to $324,800, reflecting skills, experience, and location; Apple offers comprehensive benefits, employee stock programs, relocation support, and ongoing education reimbursement.