Wafer-Level ATE Automation Engineer – LIV/LED

Avicena Tech; Sunnyvale (CA); On-site; USD 110,000 - 160,000; Full time

Job summary

Avicena Tech in Sunnyvale, CA is seeking an Automated Test Engineer to own software and hardware for our custom ATE used in wafer-level ASIC and uLED testing. You will develop test programs, debug probe cards, and analyze data to improve yield.

You will build automated test flows, create dashboards, support production, and drive root-cause analysis for test failures, working with hardware and software teams to improve reliability and test coverage.

Qualifications

• BS or MS in Electrical Engineering or related field.
• 1–4 years in semiconductor test engineering/ATE development.
• Strong proficiency in Python.
• Experience debugging hardware–software interactions.
• Experience with parametric/functional testing and yield concepts.

Responsibilities

• Develop, maintain, and extend software and scripting for custom ATE platforms.
• Design and implement automated test flows for wafer-level tests.
• Debug test failures across hardware and software stacks.
• Collaborate with hardware engineers to validate probe card designs and connections.
• Integrate new instruments and build data pipelines for LIV and parametric measurements.
• Create dashboards/reports for engineering and operations and support production.

Skills

Python

Data analysis (Python/Pandas)

Test automation

SW/HW debugging

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

SMUs

Oscilloscopes

DAQ systems

Job description

Avicena Tech in Sunnyvale, CA is seeking an Automated Test Engineer to own software and hardware for our custom ATE used in wafer-level ASIC and uLED testing. You will develop test programs, debug probe cards, and analyze data to improve yield.

You will build automated test flows, create dashboards, support production, and drive root-cause analysis for test failures, working with hardware and software teams to improve reliability and test coverage.