Location
Rowland, CA (Onsite)
Position Summary
The Wafer Fab Process Technician serves as a key production and technical leader whose primary responsibility is running volume production in support of daily wafer fabrication schedules, while also ensuring process stability, recipe control, and yield performance across InP photonic device lines, specifically InP Buried Heterostructure (BH) DFB lasers and BH Gain Chips (GC). The majority of this role's hands‑on time is spent operating the photolithography module (coat/develop track systems, steppers/scanners, and associated litho metrology) to keep volume production lots moving on schedule, with additional ownership of wet etch steps, including stripe and Mesa etch, supporting MOCVD epitaxial regrowth of InP current‑blocking layers used to form the buried heterostructure.
Responsibilities
Photolithography & Wet Etch Production Operations (50%)
- Serve as the primary production technician for the photolithography module, executing coat, expose/align, develop, and descum process steps to keep InP BH DFB laser and BH GC wafer lots moving through volume production on schedule
- Operate and monitor litho track (coat/develop) systems and steppers/scanners, maintaining critical dimension (CD), overlay, and film thickness within specification for every lot
- Execute wet etch steps, including stripe etch and Mesa etch, that directly support MOCVD epitaxial regrowth of InP current‑blocking layers for buried heterostructure formation; control etch time, temperature, and chemistry to hold mesa profile, undercut, and etch depth targets
- Perform wet bench operations including dielectric mask removal, resist strip, and pre‑regrowth surface cleans, and maintain wet bench chemistry through scheduled bath changes, concentration checks, and etch‑rate monitors
- Prioritize and sequence hot lots, engineering wafers, and standard production lots in the litho and wet etch bays to sustain high tool utilization and meet daily/weekly throughput targets
- Perform in‑line CD, overlay, etch depth, and defect inspection and first‑wafer/first‑lot qualification checks prior to releasing lots downstream
- Troubleshoot routine litho tool, wet bench, and process issues in real time to minimize downtime and protect production schedule adherence
Advanced Process Troubleshooting & Root Cause (20%)
- Lead root‑cause investigation for process excursions and drift across assigned process modules (e.g., litho CD shift, resist adhesion or defectivity, wet etch rate drift, mesa profile or undercut variation)
- Design and run targeted process checks (short‑loop wafers, engineering splits) to isolate root cause
- Partner with Process Engineering on corrective action design and verification
Process Control & SPC Ownership (20%)
- Own SPC control charts and control‑limit reviews for assigned process area, including photolithography CD, overlay, and wet etch rate and depth metrics
- Own and maintain process recipes and POR documentation for assigned process area, with emphasis on photolithography track and expose recipes and wet etch procedures
- Evaluate and implement engineering‑approved recipe changes; verify post‑change process stability
- Support qualification of new or modified process steps
DOE, Qualification & Training Support (10%)
- Support execution of DOEs, process qualifications, and NPI process runs
- Train and mentor Operators on photolithography and wet etch production operation, chemical handling, process control methods, and troubleshooting technique
Minimum Qualifications
- Associate degree in electronics, chemistry, materials science, or related technical field preferred; equivalent experience considered
- 5 - 10 years of experience in semiconductor/photonics wafer processing, with direct III‑V/InP process experience
- Direct, hands‑on experience operating photolithography track systems and steppers/scanners in a high‑volume production environment strongly preferred
- Hands‑on wet etch and wet bench experience on III‑V materials (e.g., InP, InGaAsP) preferred
- Strong working knowledge of photolithography (coat/develop track, expose/align, CD and overlay control), wet etch, and in‑line fab process steps
- Hands‑on proficiency operating litho and metrology tools (CD‑SEM, overlay, defect inspection, profilometry) in a volume production setting
- Working knowledge of wet etch chemistries, selectivity, and etch profile control for III‑V semiconductors and dielectric masks
- Ability to independently lead complex processes of troubleshooting and root‑cause investigations
- Demonstrated ability to sustain lot throughput and cycle‑time targets in a high‑volume photolithography p