Staff Process Engineer - Backside Processing, CMP & Thermal

NOKIA; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Nokia Optical Networks seeks an experienced Staff Process Engineer to lead backside processing, thinning, CMP, and thermal processing for InP photonic IC manufacturing. You will own thinning technologies, CMP planarization, and thermal recipes while collaborating with multiple engineering teams to deliver robust, manufacturable solutions.

The role demands strong ownership, 24x7 production support, and the use of DOE/SPC/data analytics to optimize process capability and yield.

Qualifications

• MS or PhD in Materials Science, Mechanical, Electrical, Chemical, Physics, or related field.
• BS with 5+ years in semiconductor/photonic manufacturing also considered.
• Strong experience in wafer thinning, backside processing, CMP, thermal processing.
• Experience with semiconductor process development, integration, yield improvement, and production support.
• Working knowledge of polishing systems, grinding equipment, furnace systems, RTP tools, process control methodologies, and materials characterization techniques.
• Demonstrated experience using DOE, SPC, JMP, statistical analysis, and data‑driven problem solving.
• Strong ownership mindset with demonstrated ability to drive projects independently and deliver measurable business impact.
• Excellent troubleshooting and cross‑functional collaboration skills.

Responsibilities

• Develop, qualify, and sustain backside wafer processing, wafer thinning, lapping, grinding, CMP, and thermal processes for InP photonic IC manufacturing.
• Own and optimize wafer thinning technologies including mechanical grinding, lapping, polishing, stress relief, and final substrate thickness control.
• Develop and optimize CMP processes for planarization, surface finish improvement, thickness control, defect reduction, and yield enhancement.
• Own thermal processes including annealing, alloy formation, furnace processing, RTP, bake, and temperature‑sensitive material integration.
• Optimize metrics including wafer thickness uniformity, TTV, surface roughness, planarity, bow/warp, defectivity, thermal stability, and device performance.
• Drive defect reduction, yield improvement, and process capability using DOE, SPC, advanced analytics, and statistical process control.
• Perform root‑cause analysis and implement corrective actions for process excursions, wafer breakage, polishing defects, thermal non‑uniformity, equipment failures, and integration challenges.
• Analyze processes from a first‑principles physics‑based approach to understand wafer mechanics, polishing, thermal interactions, and material behavior.
• Collaborate with lithography, wet/dry etch, thin film, metallization, reliability, and device engineering teams to optimize process integration.
• Lead evaluations of new consumables, slurries, pads, grinding wheels, thermal recipes, and process technologies.
• Partner with equipment vendors and materials suppliers on hardware improvements, process optimization, reliability enhancements, and cost‑of‑ownership initiatives.
• Support technology transfer from development to manufacturing while maintaining process stability and manufacturability.
• Provide rapid response and leadership during process excursions and production events.
• Support 24x7 manufacturing environment through escalation, troubleshooting, and on‑call support.
• Utilize AI‑enabled engineering tools, automation, and data analytics to improve development efficiency and manufacturing performance.

Skills

Wafer thinning

Backside processing

CMP

Thermal processing

DOE

SPC

Data analytics

AI-enabled tools

Root-cause analysis

Cross-functional collaboration

Education

MS/PhD in Materials Science/Engineering

BS with 5+ years semiconductors/manufacturing

Tools

Polishing systems

Grinding equipment

Furnace systems

RTP tools

Endpoint methodologies

Metrology techniques

DOE/SPC/JMP

Job description

At Nokia Optical Networks, advanced photonic technologies become scalable products powering the world's communication infrastructure. Our team develops and manufactures cutting-edge Indium Phosphide (InP) Photonic Integrated Circuits (PICs), enabling coherent optics, high-speed transceivers, tunable lasers, optical amplifiers, and next-generation networking solutions.

As a Staff Process Engineer - Backside Processing, CMP & Thermal, you will lead the development, optimization, qualification, and sustainment of wafer thinning, backside processing, chemical mechanical polishing (CMP), and thermal processing technologies critical to advanced photonic device manufacturing. You will work hands‑on with process equipment, consumables, materials, and metrology systems while collaborating with device, integration, lithography, etch, thin film, reliability, and manufacturing teams to develop robust, manufacturable process solutions.

The successful candidate will demonstrate strong technical leadership, a high degree of ownership, enthusiasm for manufacturing excellence, and the ability to provide fast, effective support for a 24x7 production operation.

• Develop, qualify, and sustain backside wafer processing, wafer thinning, lapping, grinding, CMP, and thermal processes for InP photonic integrated circuit manufacturing.
• Own and optimize wafer thinning technologies including mechanical grinding, lapping, polishing, stress relief, and final substrate thickness control.
• Develop and optimize CMP processes for planarization, surface finish improvement, thickness control, defect reduction, and yield enhancement.
• Own thermal processes including annealing, alloy formation, furnace processing, RTP (Rapid Thermal Processing), bake processes, and temperature‑sensitive material integration.
• Optimize critical process metrics including wafer thickness uniformity, total thickness variation (TTV), surface roughness, planarity, bow/warp, defectivity, thermal stability, and device performance.
• Drive defect reduction, yield improvement, and process capability enhancement using DOE, SPC, advanced analytics, and statistical process control methodologies.
• Perform root‑cause analysis and implement corrective actions for process excursions, wafer breakage, polishing defects, thermal non‑uniformity, equipment failures, and integration‑related challenges.
• Analyze processes from a first‑principles, physics‑based approach to understand wafer mechanics, polishing mechanisms, thermal interactions, and material behavior.
• Collaborate closely with lithography, wet etch, dry etch, thin film, metallization, reliability, and device engineering teams to optimize overall process integration.
• Lead evaluations of new consumables, slurries, pads, grinding wheels, thermal recipes, and process technologies.
• Partner with equipment vendors and materials suppliers on hardware improvements, process optimization, reliability enhancements, and cost‑of‑ownership initiatives.
• Support technology transfer from development into manufacturing while maintaining process stability and manufacturability.
• Provide rapid response and technical leadership during process excursions and production‑impacting events.
• Support a 24x7 manufacturing environment through issue escalation, troubleshooting, and on‑call support when required.
• Utilize AI‑enabled engineering tools, automation, and advanced data analytics to improve process development efficiency and manufacturing performance.

• M.S. or Ph.D. in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, Physics, or a related technical discipline.
• B.S. degree with 5+ years of semiconductor, photonics, or advanced manufacturing experience will also be considered.
• Strong experience in wafer thinning, backside processing, CMP, thermal processing, and related semiconductor manufacturing technologies.
• Experience with semiconductor process development, integration, yield improvement, and production support.
• Working knowledge of polishing systems, grinding equipment, furnace systems, RTP tools, process control methodologies, and materials characterization techniques.
• Demonstrated experience using DOE, SPC, JMP, statistical analysis, and data‑driven problem solving.
• Strong ownership mindset with demonstrated ability to drive projects independently and deliver measurable business impact.
• Excellent troubleshooting and root‑cause analysis skills.
• Ability to prioritize effectively and respond quickly to manufacturing challenges.
• Strong communication and collaboration skills in cross‑functional technical environments.
• Familiarity with AI‑enabled engineering tools and modern data analytics methods.

Preferred Qualifications

• Hands‑on experience with wafer grinding, lapping, CMP, polishing, substrate thinning, furnace processing, RTP, annealing, and wafer handling technologies.
• Experience processing InP, GaAs, silicon photonics, III‑v semiconductors, and advanced optoelectronic devices.
• Understanding of wafer mechanics, stress management, breakage reduction, thermal budget control, and backside process integration.
• Experience optimizing CMP consumables including slurries, polishing pads, conditioners, and endpoint methodologies.
• Experience with process characterization techniques including profilometry, interferometry, surface roughness measurement, SEM analysis, thickness metrology, bow/warp measurement, and defect inspection.
• Experience with high‑volume manufacturing support, process transfer, and factory ramp activities.
• Experience collaborating with equipment suppliers and technology …? ... ???
• Passion for manufacturing excellence and continuous improvement.
• Proven success balancing long-term technology development objectives with urgent production support requirements.
• Strong sense of urgency, accountability, and commitment to supporting production and customer requirements.