VLSI Design Engineer – Timing/ASIC, Equity Eligible

Broadcom; Fort Collins (CO); On-site; USD 129,000 - 207,000; Full time

Job summary

Broadcom is seeking an experienced timing/STA engineer in Fort Collins to tackle significant timing challenges in high-end VLSI/ASIC designs. You will work with global teams to analyze, constrain, and optimize timing paths, RC networks, and signal integrity while producing clear timing diagrams and reports.

The role requires strong TCL scripting, expertise in PrimeTime/Tempus, and the ability to communicate across geographies. A BS/MS in EE/CE with extensive experience is expected.

Qualifications

• BS or MS in Electrical/Computer Engineering with 12+ or 10+ years related experience.
• Expertise in VLSI/ASIC physical design and STA.
• Experience with PrimeTime or Tempus and timing constraints.
• Strong cross-geography communication and data organization.
• Proficient in TCL; other languages helpful.

Responsibilities

• Analyze complex timing issues and develop robust solutions.
• Create and debug timing constraints and generate timing reports.
• Collaborate with global teams across geographies and time zones.
• Mentor junior engineers and supervise activities as needed.
• Develop timing diagrams and validate RC and signal integrity impacts.

Skills

VLSI/ASIC physical design

PLL/clock networks

Flip-flops/latches/memories/CMOS gates

Static timing analysis (PrimeTime/Cad/

Timing constraints & reports

STA concepts

RC networks timing propagation

Signal integrity & crosstalk

Setup/hold timing checks

Timing diagrams

Variation modeling (POCV/SOCV/LVF)

MIS - multi-input switching

Liberty timing models (CCS/ECSM/NLDM)

Path-based analysis (PBA)

Location aware timing derates (LOCV/SO

SPICE analysis

TCL scripting

Python/Ruby/Bash scripting

Communication and data presentation

Education

BS in Electrical Engineering or Computer Engineering

MS in Electrical Engineering or Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

SPICE tooling

Job description

Broadcom is seeking an experienced timing/STA engineer in Fort Collins to tackle significant timing challenges in high-end VLSI/ASIC designs. You will work with global teams to analyze, constrain, and optimize timing paths, RC networks, and signal integrity while producing clear timing diagrams and reports.

The role requires strong TCL scripting, expertise in PrimeTime/Tempus, and the ability to communicate across geographies. A BS/MS in EE/CE with extensive experience is expected.