VLSI ASIC Verification Engineer

Broadcom, Inc.; Mendota Heights (MN); On-site; USD 110,000 - 176,000; Full time

Job summary

Broadcom, Inc. seeks a detail-oriented VLSI ASIC Verification Engineer to own the functional verification of complex digital blocks. You will build scalable UVM testbenches, drive constrained-random and assertion-based verification, and ensure zero-bug tape-outs.

You will analyze specifications, develop modular verification environments, and implement coverage models to achieve 100% closure before tape-out. Experience with AMBA protocols and RC/functional verification is essential.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years hands-on ASIC/SoC/IP verification experience.
• Deep proficiency in SystemVerilog and UVM architectures (agents, drivers, monitors, scoreboards, virtual sequences).
• Strong knowledge of AMBA protocols (AXI, AHB, APB) and memory/DMA controllers.
• Proven CRV, functional coverage closure, and SVA verification experience.
• Hands-on with industry-standard EDA tools (VCS, Xcelium/Incisive, Questa, Verdi).
• Scripting: Python, Tcl, and Perl for automation.

Responsibilities

• Verification planning to create thorough verification plans, trace requirements, and identify edge cases.
• Design and build modular UVM testbenches for scalable verification.
• Develop constrained-random stimulus, coverage models, and scoreboards.
• Write SystemVerilog Assertions and debug RTL-to-testbench issues.
• Drive 100% functional and code coverage before tape-out.
• Maintain automated regression suites with Python, Tcl, or Perl.

Skills

SystemVerilog

UVM

Constrained-Random

Functional Coverage

SVA

Python

Tcl

Perl

AMBA AXI

AMBA AHB

AMBA APB

Memory Controllers

VCS

Xcelium

Questa

Incisive

Verdi

Education

B.S./M.S. in Electrical Engineering or Computer Engineering

Tools

Synopsys VCS

Cadence Xcelium/Incisive

Mentor/Siemens Questa

Verdi

Job description

We are looking for a detail-oriented and experienced VLSI ASIC Verification Engineer to join our silicon engineering team. In this role, you will own the functional verification of complex digital blocks and subsystems. You will build scalable, reusable UVM testbenches, drive constrained-random and assertion-based verification, and ensure zero-bug tape-outs.

Key Responsibilities

• Verification Planning: Analyze micro-architectural specifications to create comprehensive verification plans, trace requirements, and identify edge/corner cases.
• Testbench Development: Design and build modular, reusable verification environments and testbenches using SystemVerilog and Universal Verification Methodology (UVM).
• Stimulus & Scoreboarding: Develop constrained-random stimulus, functional coverage models, scoreboards, and reference models.
• Assertions & Debug: Write SystemVerilog Assertions (SVA) to catch design violations early, run simulations, debug waveforms, and root-cause RTL-to-testbench mismatches.
• Coverage Closure: Drive functional and code coverage to 100% closure prior to tape-out.
• Automation & Regressions: Maintain automated regression suites using scripting languages like Python, Perl, or Tcl.

Required Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: minimum 8 years of hands-on experience in ASIC, SoC, or IP design verification.
• Core Methodologies: Deep proficiency in SystemVerilog and UVM architectures (agents, drivers, monitors, scoreboards, virtual sequences).
• Bus Protocols: Solid working knowledge of AMBA protocols (AXI, AHB, APB) and memory/DMA controllers.
• Verification Techniques: Proven track record in constrained-random verification, functional coverage closure, and assertion-based verification (SVA).
• EDA Tools: Hands-on experience with industry-standard simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium/Incisive, Mentor/Siemens Questa, or Verdi).
• Scripting: Strong scripting skills (Ex: Python, Tcl, or Perl) for build-flow automation and regression management.

Preferred Qualifications

• Familiarity with formal verification tools and techniques.
• Processor Architectures: Hands-on verification experience with RISC-V, ARM, or x86 core or subsystem architectures.
• CPU Pipeline & Core Verification: Deep understanding of processor pipelines, branch prediction, out-of-order execution, superscalar designs, and execution units (ALU/FPU).
• Memory Subsystem Expertise: Familiarity with verifying complex memory hierarchies, including L1/L2 caches, cache coherency protocols (AMBA CHI / ACE), MMUs, and virtual memory management.
• Exposure to high-speed interfaces or external protocols (DDR, PCIe, NVMe, SATA, or SAS).

Compensation and Benefits

• The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
• As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
• Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.

We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.

We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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