Formal Verification Engineer (VC Formal/Jasper Gold)

LanceSoft, Inc.; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

LanceSoft, Inc. is seeking a Formal Verification Engineer in Austin, TX. The role focuses on hands-on use of formal verification tools such as VC Formal or Jasper Gold and requires strong SystemVerilog Assertions (SVA) and formal property specification skills.

The ideal candidate has experience with FPV, connectivity and register verification, and additional skills in scripting (TCL, Python, Perl) to automate verification flows and improve coverage of designs.

Qualifications

• Hands-on experience with formal verification tools (VC Formal or Jasper Gold).
• Strong proficiency in SystemVerilog assertions (SVA) and formal property specification.
• Experience in FPV and connectivity, register, equivalence checking, and coverage analysis.

Responsibilities

• Apply formal verification methods to complex designs using VC Formal or Jasper Gold.
• Develop and manage formal verification plans and properties.
• Automate verification flows with scripting (TCL, Python, Perl).
• Collaborate with design and verification teams to improve coverage and correctness.

Skills

SVA (SystemVerilog Assertions)

Formal verification

FPV

Connectivity checking

Register verification

Equivalence checking

Coverage analysis

Scripting (TCL, Python, Perl)

Tools

VC Formal (Synopsys)

Jasper Gold (Cadence)

Job description

LanceSoft, Inc. is seeking a Formal Verification Engineer in Austin, TX. The role focuses on hands-on use of formal verification tools such as VC Formal or Jasper Gold and requires strong SystemVerilog Assertions (SVA) and formal property specification skills.

The ideal candidate has experience with FPV, connectivity and register verification, and additional skills in scripting (TCL, Python, Perl) to automate verification flows and improve coverage of designs.