Verification Engineer 4

Managed Staffing; San Jose (CA); Presencial; USD 150.000 - 210.000; Jornada completa

Descripción de la vacante

Managed Staffing, Inc. is seeking a senior verification engineer in the San Jose area to support a complex ASIC/SoC project.

You will participate in functional verification of blocks and IP cores within CPU/GPU development, and document test plans for directed and constrained-random simulations. The role requires extensive C/C++ experience under Linux, knowledge of Verilog/SystemVerilog/SystemC, and strong debugging skills with tools like Gdb and Valgrind.

Formación

• 8-10 years of verification experience on large ASIC projects or hardware-related software/firmware experience.
• Strong background in C/C++ development in Linux environments.
• Good debugging skills with Gdb and Valgrind.
• Proficient in object-oriented programming and data structures; knowledge of STL.
• Experience with Verilog/SystemVerilog/SystemC; DPI/PLI is a plus.
• Strong analytical skills and attention to detail; excellent written and verbal communication.
• Prefer experience with SoC verification and UVM (SystemVerilog).
• Manager open to candidates around 5 years with rate adjusted to experience.

Responsabilidades

• Participate in functional verification of ASIC blocks and IP cores for CPU/GPU development.
• Collaborate with design and verification teams to understand and verify design elements.
• Document and execute test plans with directed and constrained-random tests in simulation.
• Adopt evolving industry verification methodologies within existing infrastructure.
• Be familiar with hardware modeling and/or assertion-based verification methods.

Conocimientos

C/C++ development

Linux environment

Debug tools

Object Oriented programming

Verilog/SystemVerilog/SystemC

DPI/PLI in C

Perl

Makefiles

UVM (SystemVerilog)

Herramientas

Gdb

Valgrind

Perl tooling

Makefiles

Descripción del empleo

JOB DUTIES:

• Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.


• Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.


• Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.


• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.


• Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:

• 8-10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;


• Strong background in C/C++ development in a Linux Environment;


• Strong debug skills and experience with debug tools such as Gdb, Valgrind;


• Proficient in Object Oriented programming, STL, computer architecture and data structures;


• Knowledge of Perl and Makefiles;


• Experience in Verilog/SystemVerilog/SystemC, preferred;


• Experience in C/Verilog environment using DPI/PLI, preferred;


• Strong analytical skills and attention to detail;


• Excellent written and communication skills Prefer SoC verification experience and UVM. (System Verilog)


• Manager is open to candidates around 5 years of experience with bill rate adjusted to experience.


• Pluses: Ethernet, PCIe, PHY, and DFX.