Senior Digital Verification Engineer

Efficient Computer; San Jose, Pittsburgh, Austin (CA, Allegheny County, TX); On-site; USD 160,000 - 210,000; Full time

Benefits offered by this job

401K match

Benefits

Equity program

Parental leave

Flexible work

Job summary

Efficient Computer is seeking an experienced Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout. Join a newly formed verification team and influence products and processes as we move from initial development to market release.

Based in the United States with multiple sites, you will tackle energy-efficient computing at the edge and beyond, delivering reliable verification for next-generation hardware.

Qualifications

• Bachelor's or Master's/PhD in Electrical or Computer Engineering or related field.
• 10+ years in ASIC/SoC design verification with multiple tapeout cycles.
• Expert in UVM-based testbenches and constrained-random verification.
• C/C++ for modelling or verification.
• Proven coverage closure to tapeout on complex multi-million-gate designs.
• Strong debugging of simulation failures.
• Python for test automation and regression flow.
• Clear communication of verification risk to peers and leadership.

Skills

UVM

SystemVerilog

C/C++

Python

Debugging

Communication

Education

Electrical/Computer Engineering degree

Tools

JasperGold

Job description

San Jose, CA OR Pittsburgh, PA OR Austin, TX

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

We are looking for an experienced Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Required Qualifications & Experience

• Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
• UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology
• C/C++ experience for modelling or verification.
• Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
• Debug Skills: Proven ability to debug complex simulation failures.
• Scripting & Automation: Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
• Communication: Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership.

Ways to stand out :

• Experience in Formal verification (JasperGold or similar).
• Experience building or using AI Agentic flows for DV.
• Software/Firmware based testing experience and working with software teams pre-silicon
• SoC Architecture: Understanding and experience in some of the following areas : processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
• Power aware verification and UPF

We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility.

• 401K match
• company-paid benefits
• equity program
• paid parental leave
• flexibility