ASIC Physical Design Engineer

Efficient Computer

San Francisco (CA)

On-site

USD 100,000 - 160,000

Full time

14 days+

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Benefits offered by this job

401K match

Company-paid benefits

Equity program

Paid parental leave

Flexibility

Job summary

Join a forward-thinking company at the forefront of computing innovation as a Senior ASIC Physical Design Engineer. This role offers a unique chance to influence the development of energy-efficient SoCs from initial product stages to market launch. You'll take ownership of complex physical designs, utilizing advanced techniques to ensure optimal performance and power efficiency. Collaborate closely with cross-functional teams, automate design processes, and contribute to groundbreaking technology that transforms the future of computing. If you're passionate about making a significant impact in a dynamic environment, this opportunity is for you.

Qualifications

5+ years of experience in ASIC Physical Design with a focus on low-power designs.
Proven track record in delivering RTL2GDSII for multiple tape-outs.

Responsibilities

Own the physical design of low-power designs in advanced technology nodes.
Engage with digital design team to address timing issues through design modifications.

Skills

ASIC Physical Design

Low-Power Techniques

Physical Verification

Static Timing Analysis

Scripting in TCL

Scripting in Bash

Scripting in Python

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

Synopsys

Mentor Graphics

Job description

If you are an ASIC Physical Design Engineer who wants to impact the transformation of the next evolution of computing, we would like to talk to you. Efficient is hiring a senior ASIC Physical Design Engineer with experience in backend implementation from Netlist to GDSII. We seek individuals to leverage low‑power techniques and design-technology co‑optimization in advanced technology nodes to build energy‑efficient SoCs.

This is a unique opportunity to get in at the ground level and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

Take ownership of the physical design of multi-hierarchy low-power designs in advanced technology nodes. This includes executing physical-aware logical synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, ERC, IR drop analysis, electromagnetic analysis, and physical verification.
Analyze, debug and fix placement-, cts-, routing-, and buffering- related design and flow issues, using semi-custom placement, route guides and other tool directives via scripts to converge design to PPA targets.
Own and deliver designs meeting sign-off timing targets (setup/hold across multiple corners with OCV derating) within specified power envelope while managing constraints (sdc).
Lead the integration of the partition/IP, analyze port, feedthrough, macro placements, review DRV, LVS, IR violations and adjust collateral for clean integration.
Engage with the digital design team to understand the architecture to address congestion and timing issues through design modifications and functional Engineering Change Orders (ECOs).
Engage with the DFT team to plan and provide early feedback on design decisions that relate to physical implementation.
Create scripts for EDA tools to automate tasks and enhance the throughput and quality of the physical design process.

Required Qualifications

Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience.
Proven track record of delivering block (or SoC) RTL2GDSII for multiple tape-outs in 22nm or below process technologies.
Experience with EDA flow using Cadence/Synopsys/Mentor tools for front‑end (Synthesis/LEC), back‑end (Place and Route), and verification/simulation (Physical Verification) with hierarchical design and abstraction techniques.
Hands-on experience in place & route, power and clock-tree implementation, and timing convergence of high-frequency designs.
Knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions.
Experience with low power implementation typical in industry, including advanced knowledge of UPF standard (IEEE-1801).
Excellent scripting skills in TCL, Bash and python.

Preferred Qualifications

Experience in full chip floor planning, partitioning, budgeting, and power grid planning.
Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design.
Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
Knowledge of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
Experience in validating Power Distribution Networks from package to pg grid, IR/EM: static and dynamic.
Experience in integrating analog or mixed-signal macro on top-level design.

About Efficient:

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution.

Efficient was established in 2022 as a spinout of Carnegie Mellon University and is currently building a world-class team of hardware and software engineers spanning from silicon implementation to compilers. With seed funding secured, a portfolio of patent-protected IP, and substantial progress on hardware and software development, Efficient delivered first silicon in mid-2024. Find out more about our story at https://www.efficient.computer

Working at Efficient:

We are a small, but mighty team, with team members spread across EffHQ in Pittsburgh, Silicon Valley, and New York City. We are a young company on a tremendous growth path. We aim to bring our team together, in-person often and camaraderie is key to our success. We have the tools and technology to keep us together and interactive as a remote team, as well.

We are dedicated to our core values: Adventure, Teamliness, Excellence, Impact, Determination, Integrity. Our core values define who we are as people, as a team and as a company and they are prevalent throughout our meetings, interactions, and culture.

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, flexibility, and more! We are committed to personal and professional development and strive to grow together as people and as a company.

Seniority level