Senior Technical Staff Engineer - Validation (System Design)

Microchip; San Jose (CA); On-site; USD 70,304 - 143,000; Full time

Benefits offered by this job

Wellness & medical benefits

Restricted stock grant

Employee stock purchase plan

Tuition reimbursement

401(k) retirement savings plan

Paid time off

Job summary

Microchip Technology Inc. in San Jose, CA, seeks a Senior Technical Staff Engineer - Validation (System Design) to lead FPGA-based system design, lab bring-up, and validation of partial reconfiguration use cases.

You will drive architecture, create FPGA designs, and define validation plans for new silicon products in a cross-functional environment. The candidate will write Verilog/VHDL, utilize ModelSim and Synplicity, and mentor engineers while interfacing with teams in multiple time zones.

Qualifications

• Bachelor-level or higher in electrical/computer engineering or equivalent with 15+ years of experience in FPGA/system design.
• Experience with RTL coding in Verilog and VHDL is required.
• Strong hardware architecture and lab bring-up, validation, and debug skills.
• Knowledge of high-speed serial interfaces and PCI/USB familiarity is preferred.
• Ability to mentor engineers and coordinate cross-team activities.

Responsibilities

• Lead lab bring-up and validation of FPGA-based designs and partial reconfiguration use cases.
• Define architecture and FPGA design creation leveraging IP cores for Microchip products.
• Develop system- and product-level validation plans and manage execution, dependencies, and risk.
• Provide technical guidance and mentorship to senior and junior engineers.
• Collaborate with cross-functional teams to resolve interdependencies and improve processes.

Skills

Verilog

VHDL

C/C++

System design

FPGA prototype emulation

Lab debugging

English communication

Education

BSEE / BSCS or equivalent

MSEE / MSCS preferred

Tools

ModelSim

Synplicity

Spirent Test Center

Job description

Senior Technical Staff Engineer - Validation (System Design)

Location: San Jose, CA. This role focuses on lab bring‑up and automation of FPGA design creation and validation, systems‑level design using FPGAs, and development of partial re‑configuration use cases.

Responsibilities

• Expertise in using FPGAs to create systems‑level designs, bring up and debug such systems in the lab, including validating systems‑level UCs for partial reconfiguration.
• Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
• Development of high‑level system and product‑level validation plans for new and existing silicon products, execution per plan, review of dependencies, effort estimation, and risk communication.
• Understanding hardware architectures, defining use models, and executing/overseeing system‑level design implementations required to utilize silicon features.
• Act as the technical expert on protocols using high‑speed serial interfaces in a cross‑functional team‑oriented environment.
• Write high‑quality code in Verilog, VHDL and C; maintain existing code and support regression and re‑use.
• Learn new system designs and validation methodologies; understand FPGA architectures.
• Provide technical guidance, mentor senior and junior engineers, assign and monitor tasks of employees and contractors.
• Collaborate with cross‑functional managers/teams to identify and resolve inter‑dependencies.
• Define and improve processes within the department; follow quality metrics and assess per project.
• Be willing to take regular late‑night or early‑morning calls to interface with the engineering team in India Standard Time zone, when required.
• Use AI‑based tools to automate workflows and improve FPGA design and validation processes.

Requirements / Qualifications

• BSEE / BSCS or equivalent with 15+ years of experience.
• MSEE / MSCS preferred.
• Knowledge of FPGA architectures.
• In‑depth understanding of hardware architectures, system‑level IC design implementation, and end‑use scenario creation.
• Strong technical background in FPGA prototype emulation and debug.
• Strong technical background in silicon validation, failure analysis, and debug.
• Excellent board‑level debug capabilities in a lab environment: hands‑on troubleshooting skills for digital logic and analog circuit on PCB using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g., Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal).
• Design with RTL coding in Verilog and VHDL required.
• Experience using simulation (ModelSim) and synthesis (Synplicity) tools.
• Good knowledge of validating system‑level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB.
• Familiarity with bring‑up and on‑board debug of 32Gbps SERDES.
• Hands‑on systems‑level design and debug experience with high‑speed serial communications protocols (mandatory: PHY, PCS and data‑link layer of the OSI protocol stack; desirable: transaction and upper layers).
• Experience with lab equipment: Spirent Test Center or equivalent traffic generators and checkers.
• Strong commitment to quality and customer satisfaction.
• Excellent verbal and written communication skills in English.
• Ability to travel 0‑2 times annually if required.
• Skills in C, C++ or object‑oriented programming required.
• Embedded firmware development experience.
• Knowledge of JTAG, SVF and 1532 standards and STAPL programming desirable.
• Experience with Python/PERL/TCL scripting.

Preferred Qualifications

• Familiarity with high‑speed SERDES controllers using 32Gbps PCS, PMA: Ethernet 1–400 Gbps, (U)S(X)GMII, Interlaken, OTN OTUx, SONET/SDH, (E,X,XGS,NG)-PON, 100G‑EPON.
• Experience with video interfaces: SDI‑SD/HD/3GHD, SDI (5.94, 11.88 Gbps), DisplayPort (6.48–25.92 Gbps), HDMI (3.96–42.66 Gbps).
• JESD204C experience.
• Design and debug experience for additional high‑speed protocols: Hybrid Memory Cube, CPRI Rate 1–10+, Serial Rapid IO 4.1, USB 3.0, SATA I–III, Fiber Channel, CoaXpress.

Percentage of Time Spent

• Documentation – 15%

Essential Physical Functions and Working Conditions

• 50 % work in front of computer.
• 50 % work in the lab.
• Wellness & medical benefits effective on your first day.
• Gold standard in medical, prescription drug, dental & vision benefits.
• Quarterly employee cash bonus plan.
• Restricted stock grant.
• Employee stock purchase plan.
• Tuition reimbursement.
• 401(k) retirement savings plan.
• Spending accounts.
• Life insurance.
• Long‑term care.
• Legal.
• Employee assistance plan.

Paid Time Off

• Vacation pay.
• Absence time – sick pay.
• 10 paid holidays.

Export Controls

This job requires access to technology, materials, software or hardware that is controlled by the export laws of the United States. Candidates must provide proof of either U.S. citizenship, permanent U.S. residency or classification as a protected individual as defined in 8 USC 1324b(a)(3).

Travel Time

0 % – 25 %

Physical Attributes

• Carrying, feeling, handling, hearing, other, reaching, seeing, talking, works alone, works around others.

Pay Range

Annual base salary range: $70,304 – $143,000 (dependent on location, skills and experience).

Equal Employment Opportunity

Microchip Technology Inc. is an equal‑opportunity/affirmative‑action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.