Technical Staff Engineer - Analog Design (SRAM Design)

Microchip Technology Inc.; San Jose (CA); On-site; USD 91,000 - 232,000; Full time

Job summary

Microchip Technology Inc. is seeking a Technical Staff Engineer for the design of multiport SRAM blocks in San Jose, California. The role involves collaborating with various teams to deliver advanced FPGA products. Ideal candidates will have a minimum of 12 years of experience in SRAM design and proficiency in SPICE simulation.

The position offers a comprehensive benefits package, and the annual salary ranges from $91,000 to $232,000, dependent on experience and location.

Qualifications

• 12+ years of experience in custom SRAM design or memory circuit design.
• Proficient in yield impact, reliability, and power analysis.
• Self-motivated and proactive team player.

Responsibilities

• Define and optimize SRAM block for speed and low power.
• Run experiments to evaluate PPA trade-offs.
• Simulate and analyze critical paths and features.

Skills

SPICE simulation proficiency

Custom design EDA tool set

Analytical skills

Communication skills

Scripting and simulation management

Education

Bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science

Master's degree in Computer Engineering, Electrical Engineering, or Computer Science

Job description

Technical Staff Engineer – Analog Design (SRAM Design)

Location: San Jose, California

Microchip Technology Inc. is a leading provider of embedded control applications. The successful candidate will be responsible for the design of complex, multiport SRAM blocks for use in advanced and low power FPGA devices. In this role, you will work within a team of circuit design engineers and collaborate with architecture, ASIC, firmware, verification, and test teams to help deliver industry-leading FPGA products.

Responsibilities

• Define, estimate, develop, and optimize full custom high speed SRAM block for speed, low power, area, and feature set
• Estimate speed and power for various memory configurations and memory cell types
• Define internal memory array architecture for redundancy, ECC compliance, and optimal speed with lowest power
• Analyze projected SRAM yield per device versus redundancy requirements
• Run experiments using memory compilers from EDA vendors for embedded memories to evaluate PPA trade-offs of device mix
• Creation and verification of circuit schematics and functional Verilog models
• Simulate and evaluate SRAM cell for cell stability, write and read margin, minimum cell operating and state retention supply level, and noise margin
• Simulate and analyze critical paths and all features and functions
• Optimize memory array and non-array logic transistor sizes and Vt selection for lowest possible dynamic and standby power
• Develop and optimize sense amps for reliable operation, high speed, low power, and sufficient noise margin
• Design testability circuitry and define SRAM test requirements
• Write technical specifications and participate in formal reviews of other block specifications
• Contribute to datasheet development through block characterization
• Engage in design and verification of other circuit blocks outside of SRAM
• Support verification and timing characterization teams
• Drive and participate in silicon validation of SRAM blocks for functionality and performance

Requirements / Qualifications

• Bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science
• 12+ years of experience in custom SRAM design and/or memory circuit design
• High degree of SPICE simulation proficiency
• Adept at leveraging full custom design EDA tool set
• Demonstrated competency in scripting, managing simulation queues, data capture and analysis
• Proficient in simulating and analyzing yield impact, reliability, and power
• Ability to support layout, verification, timing characterization, and software model developers
• Ability to develop and test Verilog simulation model and compare back to SPICE based model
• Excellent analytical, communication (written and verbal), and documentation skills
• Self-motivated and proactive team player
• Attention to detail and ability to drive tasks to completion independently in timely manner

Preferred Qualifications

• Master's degree in Computer Engineering, Electrical Engineering, or Computer Science
• Experience in analog and full custom design
• Experience in FPGA or ASIC development
• Experience in functional verification and timing characterization
• Experience in low power design including dual rail, array biasing, dynamic low power mode switching (sleep, power gating, column array muxing)
• Experience in OCV timing and yield variation analyses using Solido and Monte Carlo

Travel Time

0% - 25%

Physical Attributes

Feeling, Hearing, Other, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements

10% sitting, 10% walking, 80% sitting, 100% in doors; Usual business hours

Pay Range

The annual base salary range for this position, which could be performed in the US, is $91,000 - $232,000. Range is dependent on numerous factors including job location, skills and experience.

Equal Employment Opportunity

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.