System IP Design Verification Engineer

Ursus; Austin (TX); On-site; USD 100,000 - 125,000; Full time

Job summary

An established industry player is seeking a skilled System IP Design Verification Engineer to join their innovative team in Austin. This role demands a strong technical background in design verification, with hands-on experience in creating test benches and driving best practices. You'll work closely with cross-functional teams to ensure the accuracy and efficiency of high-performance products. If you're passionate about contributing to cutting-edge technology and thrive in a collaborative environment, this opportunity is perfect for you. Join a forward-thinking company that values your expertise and offers a dynamic work environment.

Qualifications

• 12+ years experience in design verification is required.
• Expert coding skills in Testbench and coverage closure are essential.
• Experience with SystemVerilog and UVM is a must.

Responsibilities

• Architect and build reusable test benches from scratch.
• Collaborate with designers to verify design correctness.
• Develop assertions, checkers, and perform gap analysis.

Skills

Design Verification

Testbench Development

SystemVerilog

UVM

ARM Protocols

Git Version Control

Unix Scripting

Python Scripting

Communication Skills

Education

PhD in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

BS in Electrical or Computer Engineering

Tools

Git

Unix

Perl

Python

Job description

JOB TITLE: System IP Design Verification Engineer
LOCATION: Onsite in Austin, TX or San Jose, CA
DURATION: 6 months
PAY RANGE: $90-100/hour
TOP 3 SKILLS:

• PhD/MS/BS in Electrical or Computer Engineering
• 12+ years industry experience in a design verification role
• Expert hands-on coding skills in Testbench, Stimulus, checkers development, and coverage closure.

COMPANY:
Our client, a multinational electronics company, is recruiting for a System IP Design Verification Engineer. If you meet the qualifications listed, please Apply Now!

Description:
Samsung is a world leader in Memory, LCD, and System LSI technologies that has the vision and commitment to invest in the future of technology – demonstrated by the investment in the new 3nm Fab in Texas and the commitment to dramatically expanding design activities across GPU, System IP, and SoC Architecture.

We are currently looking for exceptional hardware verification engineers to join our System IP team in our Austin, TX, R&D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. The system IP team develops proprietary coherent interconnect and memory controller IPs deployed in many high-volume products.

Job Description:
As a Senior Staff System IP Design Verification Contractor, you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.

Key responsibilities include:

• Architecting and building reusable test benches from scratch
• Proposing and driving best practices/methodologies/automation that can improve productivity
• Owning key features and timely execution of tasks as per milestones
• Experience with GLS (gate level simulation)
• Creating test plans as per specifications and presenting to various stakeholders
• Working with designers to resolve any specification issues
• Creating test benches, verification environments, stimulus, and tests
• Collaborating with designers to verify the correctness of a design feature and resolve failures
• Developing assertions, checkers, covergroups, and SystemVerilog constraints
• Debugging and root causing functional failures from regressions
• Analyzing code and functional coverage results, performing gap analysis
• Working with the SoC team to debug functional failures during IP bringup and feature execution
• Collaborating with Physical design teams, running and debugging gate-level simulations
• Collaborating with Performance verification teams to assist with co-simulation testbench bringup
• Bringup power-aware verification with UPF
• Assisting with Silicon bringup and root causing failures

Requirements:
Minimum requirements:

• PhD/MS/BS in Electrical or Computer Engineering
• 12+ years industry experience in a design verification role
• Expert hands-on coding skills in Testbench, Stimulus, checkers development, and coverage closure
• Experience with System Verilog, UVM, or equivalent
• Knowledge of ARM protocols or equivalent protocols (CHI, AXI, ACElite, APB)
• Experience with Git version control, Unix/Perl/Python scripting
• Good written and verbal communication skills
• Experience with GLS, power vector generation

Nice-to-have skills:

• Formal verification skills will be a plus
• Combined experience with coherent interconnect, caches, and LPDDR memory controllers will be a plus

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