Strategic TPM: EDA & Infra, Part-Time Onsite

Ampere Computing

Santa Clara (CA)

On-site

USD 129,000 - 193,000

Part time

14 days+
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Job summary

Ampere Computing is seeking a Technical Program Manager for a part-time, six-month staff augmentation role in the IT/engineering infrastructure domain. This position supports cross-functional programs spanning engineering, EDA, security, and cloud operations from Ampere's Santa Clara, CA office.

The ideal candidate has 8+ years in technical program management, with strong knowledge of chip-design environments, cloud concepts, and risk mitigation.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
  • At least 8 years of experience in technical program management or engineering program management.
  • At least 5 years of experience leading technical teams or cross-functional programs.

Responsibilities

  • Lead complex cross-functional programs across engineering, IT, EDA, and cloud operations.
  • Define objectives, scope, milestones, dependencies, resources, and success metrics.
  • Develop integrated project plans, roadmaps, schedules, risk registers, and communication plans.
  • Coordinate with engineering, infrastructure, security, and business stakeholders.
  • Manage programs through requirements, planning, execution, deployment, and post-implementation reviews.

Skills

Technical PM
Cross-functional leadership
Cloud infrastructure
EDA environments
VLSI design flows
Stakeholder communication
Risk management

Education

Bachelor's in Electrical/CS or related
5+ years leading programs

Job description

Ampere Computing is seeking a Technical Program Manager for a part-time, six-month staff augmentation role in the IT/engineering infrastructure domain. This position supports cross-functional programs spanning engineering, EDA, security, and cloud operations from Ampere's Santa Clara, CA office.

The ideal candidate has 8+ years in technical program management, with strong knowledge of chip-design environments, cloud concepts, and risk mitigation.

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