Staff Verification Engineer – Digital & Formal (UVM, UPF)

Infineon Technologies AG; Gorham Township (OH); On-site; USD 120,000 - 180,000; Full time

Job summary

Infineon Technologies AG is seeking a Staff Engineer Digital Functional Verification to lead the development of UVM-based verification environments and test scenarios using SystemVerilog. You will ensure efficient verification with constrained-random techniques and apply UPF-based low-power verification within a global, cross-functional team.

The role emphasizes collaboration across business units, leadership in verification methodology, and continuous improvement to deliver high-quality

Qualifications

• Degree in Electrical Engineering, Computer Science or similar.
• 5+ years in digital/mixed-signal verification and formal verification.
• Proficient in SystemVerilog and UVM.
• Knowledge of UPF/PA is a plus.

Responsibilities

• Develop UVM-based verification environments for ICs.
• Create test scenarios using SystemVerilog and constrained-random testing.
• Apply formal verification methods and drive know-how exchange.
• Define verification plans, tracking, and reporting at module level.
• Verify low-power aspects using UPF and manage verification activities across sites.

Skills

SystemVerilog/UVM

Formal Verification

Metric Driven Verification

English Fluency

Education

Electrical Engineering / Computer Science degree

Tools

Cadence verification software

UPF

Job description

Infineon Technologies AG is seeking a Staff Engineer Digital Functional Verification to lead the development of UVM-based verification environments and test scenarios using SystemVerilog. You will ensure efficient verification with constrained-random techniques and apply UPF-based low-power verification within a global, cross-functional team.

The role emphasizes collaboration across business units, leadership in verification methodology, and continuous improvement to deliver high-quality