Senior SOC Physical Design Engineer

Qualcomm; Austin (TX); On-site; USD 124,000 - 173,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a candidate to independently plan and perform moderately-defined Physical Design responsibilities for high-speed DDR, graphics, and SOC flows.

The role focuses on optimizing power, performance, and methodology while supporting PDN and timing closure. Responsibilities include floor planning, clock tree synthesis, place-and-route, LVS/DRC checks, and cross-functional collaboration to drive tapeout readiness and signoff.

Qualifications

• Master's degree in Electrical Engineering or related field.
• Experience with physical design flows and methodology.
• Knowledge of LVS/DRC and design-for-manufacturing/yield checks.

Responsibilities

• Plan and perform physical design activities for high-speed DDR, graphics, and SOC flows.
• Conduct Floor Planning and Clock Tree Synthesis as part of PD design.
• Execute Place and Route steps and ensure PDN integrity.
• Perform timing analysis and closure to meet signoff targets.
• Support cross-functional engineering reviews and drive tapeout readiness.

Skills

Floor Planning

Clock Tree Synthesis

Place and Route

PDN

Timing analysis

Education

Master's Degree in Electrical Engineering

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

This individual independently plans, performs the moderately-defined responsibility for the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance.

Responsibilities include:

• Floor Planning
• Clock Tree Synthesis
• Place and Route
• PDN
• Timing analysis and closure

Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels.

Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout.

Acts as a strong contributor at design reviews and project meetings.

Requirements / Qualifications:

Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.

Pay:

Pay Range: $124,019.00 - 173,400.00/year

Equal Opportunity Employer:

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EEO Statement:

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Company Policies:

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