Staff SoC DFT Engineer, HBM

Micron; Richardson (TX); On-site; USD 131,000 - 161,000; Full time

Job summary

Micron Technology's Heterogeneous Integration Group seeks a senior SoC test architect to own DFT for high-bandwidth memory base-die designs. You will define DFT architecture early in the design cycle and implement scan, MBIST/LBIST, and boundary scan within RTL-to-GDS flows, collaborating with RTL, STA, and physical design teams.

This role offers influence on pre-silicon bring-up and post-silicon diagnostics across next-gen HBM generations, focusing on testability, manufacturability, and

Qualifications

• Strong hands-on SoC DFT architecture and implementation experience.
• Experience across RTL-to-GDS flows with synthesis, STA, and physical design.
• Proficiency with EDA tools from Siemens, Synopsys, Cadence for DFT.
• Bachelor's degree in Electrical/Computer Engineering or equivalent.
• 7+ years in SoC design, DFT, or implementation.

Responsibilities

• Own SoC-level DFT structures and their implementation, including scan, MBIST/LBIST, boundary scan (JTAG), and ATPG.
• Define and drive DFT architecture early in the design cycle, aligned with SoC integration, floorplanning, timing, and PD requirements.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels with RTL/SoC teams.
• Complete and sign off DFT flows, including linting, CDC checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement, routing, timing closure, and DRC/LVS signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability and post-silicon bring-up.
• Partner with CAD/methodology teams to standardize DFT flows and mentor engineers.

Skills

SoC DFT architecture

ATPG

MBIST/LBIST

RTL-to-GDS flows

EDA tools (Siemens, Synopsys, Cadence)

7+ years experience

Education

Bachelors in Electrical/Computer Engineering

Tools

Siemens

Synopsys

Cadence

Job description

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry.

You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM)

Responsibilities will include, but are not limited to:

• Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds.
• Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements.
• Implement and integrate DFT logic at block, subsystem, and full‑chip levels while partnering closely with register‑transfer level (RTL) design and SoC integration teams.
• Complete and sign off DFT flows, including linting, clock‑domain crossing (CDC) checks, DFT rule checks, automatic test pattern generation (ATPG) readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and design rule check/layout versus schematic (DRC/LVS) signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, smooth pre‑silicon debug, and post‑silicon bring‑up.
• Partner with computer‑aided design (CAD) and methodology teams to standardize and improve DFT flows, contribute to cross‑group technical reviews, mentor engineers as appropriate, and drive innovation for future HBM generations.

Minimum Qualifications:

• Strong hands‑on experience with SoC develop for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience working across full RTL‑to‑GDS SoC flows and collaborating with synthesis, static timing analysis (STA), and physical design teams.
• Proficiency using industry‑standard electronic design automation (EDA) tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital application‑specific integrated circuits (ASICs) or SoCs.

Preferred Qualifications:

• Experience with large, complex SoCs that integrate multiple intellectual property (IP) blocks and subsystems.
• Strong RTL debugging, design analysis, and problem‑solving skills.
• Experience using scripting languages such as Python, Tcl, or Perl for flow automation.
• Familiarity with memory systems such as dynamic random‑access memory (DRAM), high‑bandwidth memory (HBM), and related JEDEC specifications.

The US base salary range that Micron Technology estimates it could pay for this full‑time position is:

$146,000.00 - $247,000.00 a year

Additional compensation may include benefits, bonuses and equity.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job‑related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.