Principal DFT Engineer, HBM

Micron; Folsom (CA); On-site; USD 146,000 - 309,000; Full time

Benefits offered by this job

Medical coverage

Dental coverage

Vision plans

Paid time off

Paid holidays

Equity

Job summary

Micron Technology is seeking a Principal SoC DFT Engineer to own DFT architecture, implementation, and signoff for HBM base-die designs within the Heterogeneous Integration Group. Work with RTL, physical design, verification, and product engineering to enable robust test solutions from pre-silicon through tapeout and bring-up.

The role requires 7+ years in SoC DFT/implementation, with experience in scan, MBIST/LBIST, JTAG, ATPG, and full RTL-to-GDS flows using Siemens, Synopsys, or Cadence

Qualifications

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of proven experience in SoC development, DFT, or implementation for complex digital ASICs or SoCs.
• Job title and level can scale depending on experience and qualifications.

Responsibilities

• Own SoC-level DFT implementation, including scan, MBIST, LBIST, boundary scan, and JTAG architectures.
• Drive DFT architecture definition early in the design cycle with alignment to integration, timing, and physical design constraints.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels with RTL and integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT checks, ATPG readiness, and coverage.
• Collaborate with physical design to optimize DFT for placement, routing, timing closure, and signoff.
• Support pre-silicon debugging and post-silicon bring-up and yield analysis.
• Partner with CAD and methodology teams to standardize DFT flows across HBM SoC programs.

Skills

DFT architecture

MBIST

LBIST

Boundary scan

ATPG concepts

RTL-to-GDS flows

EDA tools

Python

Tcl

Perl

Education

Bachelor's degree

Tools

Siemens

Synopsys

Cadence

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip (SoC) designs. This role is part of the SoC execution team, working closely with RTL design, verification, physical design, and product engineering to ensure robust, scalable, and manufacturable test solutions from pre-silicon development through tapeout and product bring-up. (LLM)

Responsibilities

• Own SoC-level DFT implementation, including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs.
• Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
• Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up.
• Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis.
• Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.

Required Experience

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of proven experience in SoC develop, DFT, or implementation for complex digital ASICs or SoCs.
• Job title and level can scale depending on experience and qualifications.

Successful candidates for this position will have:

• Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
• Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
• Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation.

US base salary range that Micron Technology estimates could pay for this full-time position

$146,000.00 - $309,000.00 a year

Additional compensation may include benefits, bonuses and equity.

Micron benefits

We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.

Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.

Additionally, Micron benefits include a robust paid time-off program and paid holidays.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.