Staff NAND Design Engineer — RTL & Verification

Micron Technology, Inc.; San Jose (CA); On-site; USD 145,000 - 246,000; Full time

Job summary

Micron Technology, Inc. in San Jose, CA, seeks a Staff Design Engineer to craft and optimize NAND circuits for memory products.

You will interpret specifications, design architectures, and lead RTL/gate-level verification while collaborating with internal and external teams to ensure performance, quality, and reliability. The role requires 7+ years in digital circuit design, strong leadership, and experience in RTL/verification.

Qualifications

• Bachelors degree in computer/ electrical engineering or related field.
• 7+ years of experience in digital circuit design and development.
• Proven track record to meet performance, area, and power targets.
• Experience with RTL and gate-level verification processes.

Responsibilities

• Interpret device and system specifications to deliver required functionalities.
• Participate in the conception and development of new circuits.
• Define and design composition architecture specifications for new features.
• Support the creation of schematics and/or RTL blocks.
• Define best known design and verification practices and communicate them to the department.
• Perform RTL and synthesized netlist (gate level) verification at block, subsystem, and full chip level.
• Facilitate netlist bring up to achieve basic functionality.
• Deliver design simulation including post layout.
• Design verification plans for new and existing features and check desired behavior in Verilog.
• Collaborate with Product Engineering on validation plans and review silicon results.
• Assist in silicon design validation, reticle experiments, qualification, and tape-out revisions as needed.

Skills

RTL verification

Gate-level verification

Collaboration

Leadership

Education

Bachelor's degree in Computer Engineering or Electrical Engineering

Tools

Verilog

Job description

Micron Technology, Inc. in San Jose, CA, seeks a Staff Design Engineer to craft and optimize NAND circuits for memory products.

You will interpret specifications, design architectures, and lead RTL/gate-level verification while collaborating with internal and external teams to ensure performance, quality, and reliability. The role requires 7+ years in digital circuit design, strong leadership, and experience in RTL/verification.