Staff FPGA & Protocol Logic Design Engineer

Teledyne Energy Systems, Inc.; Milpitas (CA); On-site; USD 142,000 - 189,000; Full time

Job summary

Teledyne LeCroy seeks a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture and analysis. You will work on FPGA-based systems decoding PCIe, USB, Ethernet in real time, coordinating with cross-functional teams to deliver cutting-edge test and measurement solutions.

The role emphasizes Verilog/SystemVerilog RTL design, FPGA toolchains, and UVM-based verification with a focus on low latency, high bandwidth, and robust debugging capabilities.

Qualifications

• BS in EE, CS or Computer Engineering required.
• MS in EE is a plus.
• 7+ years of experience in digital logic design for FPGA or ASIC.
• Strong proficiency in Verilog/SystemVerilog RTL design.
• Experience with PCIe, CXL, NVMe, USB, SAS, SATA.

Responsibilities

• Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management.
• Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency.
• Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimization.
• Integrate PCIe IP cores, DMA engines, and custom protocol decoders.
• Build SystemVerilog/UVM testbenches for block and system-level verification.
• Conduct simulation, waveform analysis, and functional coverage to ensure robust design.
• Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms.
• Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap).
• Create design specifications, interface documents, and verification plans.
• Participate in design/code reviews and contribute to continuous improvement of design practices.

Skills

Verilog/SystemVerilog RTL

FPGA/ASIC design

PCIe protocol

Timing closure

UVM/Verification

Education

BS in EE/CS

MS in EE is a plus

Tools

Vivado

Quartus

ModelSim/Vivado Simulator

Job description

Teledyne LeCroy seeks a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture and analysis. You will work on FPGA-based systems decoding PCIe, USB, Ethernet in real time, coordinating with cross-functional teams to deliver cutting-edge test and measurement solutions.

The role emphasizes Verilog/SystemVerilog RTL design, FPGA toolchains, and UVM-based verification with a focus on low latency, high bandwidth, and robust debugging capabilities.