Staff Logic Design Engineer: FPGA & High-Speed Protocols

Teledyne LeCroy Korea; Milpitas (CA); On-site; USD 142,000 - 189,000; Full time

Job summary

Teledyne LeCroy, a global leader in protocol analysis and test solutions, seeks a Staff Logic Design Engineer in Milpitas, CA. You will architect and implement high-performance digital logic for protocol capture, analysis, and emulation on FPGA-based systems.

You’ll work on cutting-edge PCIe, USB, Ethernet protocols with cross-functional teams to deliver industry-leading test and measurement solutions; strong Verilog/SystemVerilog, FPGA toolchains, and UVM experience are essential.

Qualifications

• BS in EE, CS or Computer Engineering required.
• MS in EE is a plus.
• 7+ years of digital logic design for FPGA/ASIC.
• Strong proficiency in Verilog/SystemVerilog RTL design.
• Experience with PCIe, CXL, NVMe, USB, SAS, SATA.
• Experience with Monitoring and/or Test & Measurement tools.
• Experience with PCIe Gen4/Gen5/Gen6 and TLP/DLLP/PHY concepts.
• Hands-on with FPGA toolchains (Vivado, Quartus) and timing closure.
• Knowledge of UVM, assertions, and simulation/debug tools (ModelSim, Vivado Simulator).
• Solid understanding of CDC, clock domain design, and reset strategies.

Responsibilities

• RTL Design & Microarchitecture Develop synthesizable RTL for high-speed protocol, packet parsing, timestamping, and buffer management.
• FPGA Development Target high-end FPGAs (Versal, Agilex); integrate PCIe IP cores, DMA engines, and protocol decoders.
• Verification & Debug Build SystemVerilog/UVM testbenches; simulation, waveform analysis, and coverage.
• System Integration Collaborate with hardware, firmware, and software teams for platform bring-up and validation.
• Documentation & Process Create design specs, interface docs, and verification plans; participate in reviews.

Skills

RTL design

Microarchitecture

Verilog/SystemVerilog

UVM

ModelSim/Vivado Simulator

CDC / clock domain

Education

BS in EE/CS/CE

MS in EE (plus)

Tools

Vivado

Quartus

Job description

Teledyne LeCroy, a global leader in protocol analysis and test solutions, seeks a Staff Logic Design Engineer in Milpitas, CA. You will architect and implement high-performance digital logic for protocol capture, analysis, and emulation on FPGA-based systems.

You’ll work on cutting-edge PCIe, USB, Ethernet protocols with cross-functional teams to deliver industry-leading test and measurement solutions; strong Verilog/SystemVerilog, FPGA toolchains, and UVM experience are essential.